Tag Archive image sensors

ByAdministrator

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

~ ~ ~

This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

ByAdministrator

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

iedm_logoBeyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 2 of ASN’s IEDM coverage, we’ll cover future device architectures. In Part 1, we had a rundown of the top SOI-based advanced CMOS papers. In Part 3 we’ll look at MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

16.2: Dual-Channel CMOS Co-Integration with Si Channel NFET and Strained-SiGe Channel PFET in Nanowire Device Architecture Featuring 15nm Gate Length

P. Nguyen et al (Leti, ST, Soitec)

 

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM 14, Paper 16.2)

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM
14, Paper 16.2)

The researchers have fabricated the first hybrid channel omega-gate CMOS nanowire (NW) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FET. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NW (LG=15 nm) with +90% ION current improvement. [110]-oriented NW is shown to be the best candidate to improve drive current under compressive strain. In this work, the strain is measured by using precession electron diffraction with a 1nm spatial resolution. Furthermore, they show that hybrid integration reduces the delay of CMOS ring oscillator (FO=3) by 50% at VDD=0.9V. Finally, they demonstrate the most aggressively scaled hybrid CMOS NWs reported to date with NW width and gate length down to 7nm and 11nm, while maintaining high drive current (687µA/µm for p-FET and 647µA/µm for n-FET) with low leakage current and excellent short-channel-control (DIBL<50mV/V).

 

20.5: Study of the Piezoresistive Properties of NMOS and PMOS Omega-Gate SOI Nanowire Transistors: Scalability Effects and High Stress Level

J. Pelloux-Prayer et al (Leti, Soitec, Tokyo Tech)

The researchers present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). They show that the downscaling of geometrical parameters doesn’t allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.

 

20.3: Direct Observation of Self-heating in III-V Gate-all-around Nanowire MOSFETs

S.H. Shin et al (Purdue U)

Multi-gate devices, such as, FinFET, Gate-all-around transistors (GAA-FET) improve 3D electrostatic control of the channel, but the corresponding increase in self-heating may compromise both performance and reliability. Although the self-heating effect (SHE) of FinFET appears significant, but tolerable, the same may not be true for GAA geometry, especially in quasi-ballistic regime where hot spots and non-classical heat-dissipation pathways may lead to localized damage. The existing reports of the SHE on the SOI, FinFET or GAA-FET have so far relied either on indirect electrical measurements with inherent temporal delays, or on optical infra-red (λ>1.5μm ) imaging that cannot resolve deep submicron features. As a result, it has so far been impossible to resolve the spatio-temporal features of SHE fully. In this paper, the researchers develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the local temperature rise of GAA-FET with different number of nanowires (NW)(ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW.

 

9.6: In-situ Doped and Tensilely Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828µA/µm, Ion/Ioff ~ 1×105, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement

I-H. Wong et al (Taiwan U)

In-situ CVD doping and laser annealing can reach [P] and tensile strain as high as 2×1020 cm-3 and 0.37%. Junctionless Ge gate-all-around nFETs with 9 nm-Wfin and 0.8 nm-EOT achieves the record high Ion of 828 µA/µm. The Ion enhancement of ~40% is achieved under the tensile strain of 0.25%.

 

27.6: Flexible High-performance Nonvolatile Memory by Transferring GAA Silicon Nanowire SONOS onto a Plastic Substrate

J.-M. Choi et al (KAIST, NASA)

Flexible nonvolatile memory is demonstrated with excellent memory properties comparable to the traditional wafer-based rigid type of memory. This  achievement is realized through the transfer of an ultrathin film consisting of single crystalline silicon nanowire (SiNW) gate-all-around (GAA) SONOS memory devices onto a plastic substrate from a host silicon wafer.

13.2: High Ion/Ioff Ge-source Ultrathin Body Strained-SOI Tunnel FETs – Impact of Channel Strain, MOS Interfaces and Back Gate on the Electrical Properties

M. Kim et al (U Tokyo)

The researchers demonstrated Ge/strained-Si hetero-junction TFETs with in-situ B doped Ge. The increase in channel strain and optimization of PMA have successfully realized high performance of steep SSmin below 30 mV/dec and large Ion/Ioff ratio over 3×107.

13.3: Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective

Q. Huang et al (Peking U)

In this paper, a novel TFET design, called Pocket-mSTFET, is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from a circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated Pocket-mSTFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Circuit-level implementation based on Pocket-mSTFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

13.4: A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

J. Zhang et al (EPFL)

The researchers demonstrate a steep subthreshold slope silicon FinFET with Schottky source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA/μm is also achieved with high Ion/Ioff ratio of 107.

 

26.2: Thin-Film Heterojunction Field-Effect Transistors for Ultimate Voltage Scaling and Low-Temperature Large-Area Fabrication of Active-Matrix Backplanes

B. Hekmatshoar et al (IBM)

Heterojunction field-effect thin-film transistors with crystalline Si channels and gate regions comprised of hydrogenated amorphous silicon or organic materials are demonstrated. The HJFET devices are processed at 200ºC and room temperature, respectively; and exhibit operation voltages below 1V, subthreshold slopes of 70-100mV/dec and off currents as low as 25 fA/um.

 

26.7 Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel for 3D IC Applications

Y.-C. Cheng et al (National Tsing Hua U, National Chiao Tung U)

The hybrid fin poly-Si channel junctionless field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of steep SS (64mV/dec), high Ion/Ioff (>107) and small DIBL (3mV/V). The devices are highly promising for future further scaling and 3D stacked ICs applications.

 

35.1: A Physics-based Compact Model for FETs from Diffusive to Ballistic Carrier Transport Regimes

S. Rakhejaet al (MIT, Purdue U)

The virtual source (VS) model provides a simple, physical description of transistors that operate in the quasi-ballistic regime. Through comparisons to measured data, key device parameters can be extracted. The VS model suffers from three limitations: i) it is restricted to short channels, ii) the transition between linear and saturation regions is treated empirically, and iii) the injection velocity cannot be predicted, it must be extracted by fitting the model to measured data. This paper discusses a new model, which uses only a few physical parameters and is fully consistent with the VS model. The new model: i) describes both short and long channel devices, ii) provides a description of the current at any drain voltage without empirical fitting, and iii) predicts the injection velocity (device on-current). The accuracy of the model is demonstrated by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

 

~ ~ ~

This is the 2nd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

 

ByGianni PRATA

TowerJazz — Interview With SVP Marco Racanelli: What’s Driving Strong SOI-Based Design Wins?

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

 

 

TowerJazzLogo_2014LR

 

 

 

 

ASN recently spoke with TowerJazz SVP Marco Racanelli about when the specialty foundry leverages SOI – and why.

Advanced Substrate News (ASN): Can you tell us briefly about TowerJazz’s overall vision and position in the market? 

Marco Racanelli (MR):  TowerJazz is the foundry leader for the manufacture of specialty semiconductor devices.  By “specialty” semiconductor devices, we mean those that require technology with some degree of specialization beyond commodity CMOS, for example in applications such as analog, RF, power, CMOS Image Sensor, and MEMS.  We invest in specialty process technology and manufacturing capacity around the world to fuel our growth (today we have manufacturing facilities in the US, Israel and Japan).

The TowerJazz fab in Newport Beach, CA.

The TowerJazz fab in Newport Beach, CA.

ASN: What kinds of chips does TowerJazz propose customers put on SOI? Why? 

MR: SOI on high resistivity substrates provides excellent RF isolation for customers working on front-end modules (FEMs) for wireless communication products.  Specifically for RF switches, thin device silicon layers result in low junction capacitance which is favorable for achieving high isolation.  We have had some customers leverage our SiGe BiCMOS technologies on SOI to integrate improved RF switching capabilities and achieve better isolation among circuit blocks.  Finally, some TowerJazz customers use thick film SOI for MEMS.  The silicon layer in SOI is used to fabricate beams for electro-mechanical structures and devices, e.g. MEMS resonators.

ASN: What are the growth drivers (end-markets, trends) for your SOI-based services? 

MR: Each generation of smart phones has required increasing numbers of RF ports to support multiple standards and functions e.g. 3G, 4G, 802.11, diversity antenna.  The need for longer handset battery life is driving implementation of RF-SOI based antenna tuner products to improve antenna efficiency.

 

Click to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

Click image to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

ASN: What are the advantages in moving to SOI-based technologies? 

MR: In some markets such as FEMs, the performance advantages of SOI are required to enable these RF products in CMOS; bulk technologies simply can’t provide the required isolation and low capacitance to meet the most demanding 4G/LTE specifications.  Thicker film SOI can support SiGe bipolar devices with significantly lower collector-to-substrate capacitance than their bulk counterparts.  In high voltage products, SOI dielectric isolation can simplify the design process, reduce latch-up risk, and allow a much more compact design than junction-isolated technologies.

Inside the TowerJazz Newport Beach Facility (Fab 3)

Inside the TowerJazz Newport Beach Facility (Fab 3)

ASN: Are there particular regions where you see especially high growth for SOI-based offerings? 

MR: We see broad adoption of SOI in all major phone platforms.  Our strongest growth and largest market for SOI is in the US although we see some Asia customers as well. The end customers are more evenly distributed between the US and Asia primarily.

ASN: Last year, you announced your RF-SOI had the industry’s best figure of merit for antenna switch and antenna tuning applications. What are you seeing there in terms of design wins? 

MR: We are seeing very strong design wins and production ramp of SOI in our factories.

 

American Semiconductor's  FleX-MCU™ product family leverages an SOI starting wafer.  (Courtesy: American Semiconductor)

American Semiconductor’s FleX-MCU™ product family leverages an SOI starting wafer.
(Courtesy: American Semiconductor)

ASN: American Semi partnered with TowerJazz on flexible ICs, which leverage SOI.  What sort of applications is that technology going into?  

MR: The potential for flexible ICs is very broad. For Aerospace and Defense, key areas of interest are ‘wearable’ circuits, introducing ICs and systems into soldiers’ field clothes and gear, creating a radar system that conforms to the entire body of an aircraft, sea vehicle, or any UAV or drone.  The ideas can be countless – the path is to reduce or eliminate the rigid form and fit of mobile electronics and integrate these electronics into a lighter weight, smaller and more flexible material.

ASN: Cavendish Kinetics announced that they’d be collaborating with you on RF-MEMS for mobile, which could be on SOI.  Is that available, and if so, can you tell us about it?

MR: We continue to work with Cavendish and have announced impressive reliability results with their devices; these are available through Cavendish directly.

ASN: Can you tell us more about the forthcoming 0.18 TS18SOI integrated power platform? 

MR: This platform is targeting a number of applications, the dominant one being in automotive and will include high-voltage devices, 0.18um CMOS for integration of digital and power management functions along with non-volatile-memory.  SOI in this case helps isolate the devices from the substrate allowing flexibility in applying voltages without turning on junctions that can lead to leakage or latch-up and in some cases helps reduce die-size by improving isolation allowing devices to be closer together.

ASN: Looking down the road, where/how do SOI-based technologies fit into your outlook for the future?  

MR: SOI particularly for RF is a significant focus for TowerJazz and we continue to invest in new technology and propagating the technology we have to multiple factories to increase capacity available to our customers.  While RF dominates our SOI consumption, we also see a good future for SOI in power management and MEMS and other sensor applications.

 

TGS2014_logo-LR

 

 

 

 

TowerJazz will be presenting its SOI and other processes at its upcoming Technical Global Symposiums (TGS) taking place in Europe (18 September 2014), the US (19 November 14) and Japan (10 December 2014). To find out more and register for TGS, please visit: http://www.towerjazz.com/tgs/

 

 

 

~ ~ ~

Dr. Marco Racanelli has served as TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group since September 2008. Previously, he served as Vice President of Technology & Engineering, Aerospace & Defense General Manager for Jazz Semiconductor.

 Prior to Jazz, Dr. Racanelli held several positions at Conexant Systems and Rockwell Semiconductor since 1996 in the area of technology development where he helped establish industry leadership in SiGe and BiCMOS and MEMS technology, and built a strong design support organization. Prior to Rockwell, Dr. Racanelli worked at Motorola, Inc., where he contributed to bipolar, SiGe and SOI development for its Semiconductor Products Sector.

 Dr. Racanelli received a Ph.D. and a M.S. in Electrical and Computer Engineering from Carnegie Mellon University, and a B.Sc. in Electrical Engineering from Lehigh University. He holds over 35 U.S. patents.

~ ~ ~

By

FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.

 

FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.

 

FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

 

The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.

 

Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.

 

FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

By

Going Up! Monolithic 3D as an Alternative to CMOS Scaling

By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti) 

The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as much calculating power as multi-million-dollar supercomputer 10 years ago! But at 28nm, it seems the race is over: Moore’s scaling is facing obstacles – parasitic phenomena, incompressible delays, energy dissipation – that can be overcome with technology, but not in a way that is economically sustainable for everyone. This is where the idea to go 3D comes in: the density and cost dictated by Moore’s Law would be achieved not by 2D shrinking but by going up into the third dimension.

Fig1_M3D_Leti_evalchall

Piling transistors on top of each other in a “3D” configuration is not new. Stacking techniques using through-silicon vias (TSVs) are currently used for CMOS image sensors, MEMS, and now 3DNAND. In these scenarios, the devices themselves are processed on separate wafers, then aligned and bonded. The TSVs are essentially copper columns added to connect the top and bottom devices. While beneficial in certain cases, the TSV approach faces its own set of challenges with respect to aligning the transistors, the comparatively wide diameters of the TSVs, the pitch and the overall thickness.

Fig2_TSVvsM3D

Monolithic 3D (M3D), which takes a very different approach to stacking transistors on top of each other, is one of the most promising alternatives approaches when going 3D. M3D aims at increasing transistor density “sequentially” – meaning within a single process flow, as opposed to the TSV approach, which is applied to die that have already been processed. Staying within the bounds of a single process flow makes M3D much more cost-effective. M3D will enable an increased density of transistors without requiring the downscaling of their individual features. M3D could also provide a gain in performance by reducing the metal wiring delay, thanks to direct contact between transistor levels. From a cost perspective, M3D appears to offer a competitive advantage over equivalent N+1 scaling nodes:  the scaling achieved in node N and even N-1 can be leveraged for another generation.

At CEA-Leti in Grenoble (France), one of the world’s most advanced microelectronics R&D centers, CMOS-device teams are exploring various routes to meet increased performance requirements of future semiconductor applications. M3D is a primary focus in the search for alternate routes to scaling, in addition to other disruptive approaches such as steep slope devices, mechanical switches based on NEMS and single electron transistors.

Fig3_LetiDeviceTechRoadmap

Leti is known for its expertise in the fields needed to demonstrate and take the industry lead in the M3D concept:

  • a strong background-related to SOI devices fabrication
  • a long history of process developments in molecular bonding of various substrates and materials, essential for creating a high-quality top active layer
  • thorough experience in 3D stacking techniques, including design-tool developments, architecture exploration and test-vehicle or full-circuit implementations.

Leti’s M3D program was first launched in 2007. In order to reach the expected performance with an acceptable time to market, M3D must be developed with close, simultaneous attention to applications, design and technology challenges. The success demonstrated since the program launch prompted Qualcomm to partner with Leti in 2014 to explore M3D technology potential for future generations of products.

 

Leti’s M3D: How it’s done

The M3D concept consists of sequentially processing:

  • processing a bottom MOS transistor layer
  • processing another MOS transistor layer on top of the bottom one with lithographic alignment between the layers
  • positioning metal lines between the two layers to allow connections between both transistor levels.
  • encapsulating the inter-metal levels in an oxide layer
  • bonding a wafer substrate to the top transistor layer using molecular bonding
  • a planarization process.

Using an SOI wafer for the top layer molecular bonding provides higher crystalline quality, greater integration density, and accurate thickness control. CEA-Leti has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.

  Screen Shot 04-09-14 at 10.35 AM

M3D Advantages

The main advantages of M3D are derived from the sequential fabrication of the various transistor layers on the same wafer. It leads to very high alignment accuracy (3D contact pitch <100nm using lithography tools adapted to 14nm production), uses high-density interconnects, and surpasses 3D-TSV performance at a competitive cost. The inter-metal levels also facilitate design partitioning and architecture exploration.

Fig5_M3DvTSVleti

Leti’s M3D approach is of particularly high value for those products that do not really benefit from scaling, especially when cost constraints are stringent. Different design simulations estimate a gain of one-node performance without scaling constraints. Once the remaining challenges are overcome, potential applications range from heterogeneous stacks (imagers, MEMS on logic) to advanced memory structures, advanced processors, programmable logic and various SOCs. All those products would benefit greatly from the added value provided by M3D:

  • High-circuit density provided by stacking active layers in 3D at minimum-contact pitch level
  • Better power dissipation (greater absorption across inter-metal levels surface)
  • Increased speed/power performance trade-off by reducing high-resistivity metal wiring length.
  • Competitive cost advantage by re-using a given node process scheme without requiring additional/new steps to achieve performance gains.

 

Fig6_LetiSlide18M3Dinterest_dec13

 

PDK & Model Availability

In addition to the M3D technology process flow development, CEA-Leti is also proposing a Predictive Design Kit (PDK) that provides a primitive M3D product design environment for integrated modeling, simulation, visualization and communication. It also includes validation tools that product designers need to benchmark M3D and explore new architecture concepts. The first M3D PDK version available from CEA-Leti will permit partners to get a first knowledge of the M3D technology, so they can run initial performance assessments regarding density, speed, power and cost.

Screen Shot 04-09-14 at 10.33 AM

Future Development

Part of CEA-Leti’s mission is to develop technologies that are ready to transfer to industry, supporting customers in both developing knowledge and implementation on the manufacturing floor. In the case of M3D, CEA-Leti is beginning to build a full ecosystem of partners to enable the rapid industrialization of this technology. Qualcomm, a world leader in wireless technologies, joined CEA-Leti in its M3D R&D program in 2014 and has committed resources to assess the feasibility of the concept.

To expand the momentum around M3D, while validating design-and-process assumptions and expected performance through prototyping demonstrators, the ecosystem should also  involve a major foundry. CEA-Leti also plans to include additional members of the semiconductor business value chain (device modeling, EDA, process tooling, test, etc.) to form a complete M3D ecosystem, and make M3D a competitive technology for industrial transfer.

In the short term, CEA-Leti is looking for interested companies to engage in an R&D program aimed at validating proof of concept of an M3D integration process flow and its related libraries for advanced CMOS nodes.

~ ~ ~

Publications reference:

  • P.Batude et al3D Monolithic Integration, IEEE 2011
  • P.Batude et al3-D Sequential Integration: a Key Enabling Technology for Heterogeneous Co-Integration of New function with CMOS, IEEE Journal on Emerging and selected topics in Circuits & Systems, 2012
    • S.Bobba et alCELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits, IEEE 2011
    • O. Turkyilmaz et al3D FPGA using high-density interconnect Monolithic Integration, DATE 2014

 

 

ByGianni PRATA

Sarnoff’s (once RCA) new SOI-based Ultra-Sense™ is a low-cost

By

Production-Worthy Backside-Illuminated Image Sensors

This SOI-based process requires no post-thinning passivation step.

Demand for better cameras in less expensive mobile phones is pushing researchers to find higher performance image sensor solutions for that cost-conscious end of the market. Last year, a research team from MagnaChip and JPL presented a paper at the International Electron Devices Meeting (IEDM 2007, Washington, DC) demonstrating the development of a production-worthy, backside-illuminated (BSI) monolithic sensor with 2.2 µm pixels. We used low-cost, standard fabrication techniques and available, mature technology modules. Compared to a conventional, frontside-illuminated (FSI) sensor, our 2-megapixel (MP) sensor exhibited comparable dark current and noise, but much higher quantum efficiency (QE) and sensitivity.

As shown in the figure, the height of the optical stack is much lower for the BSI pixel, leading to significant advantages in the effective pixel f/ (effective focal length) number. Furthermore, thanks to the high refractive index of silicon, light converges at the center of the pixel, and the optical energy is well-contained therein.

Performance of the MagnaChip 2-Megapixel Imager

Starting with SOI

We began the fabrication process with SOI wafers, which enables the oxide to act as an etch-stop for accurate backside thinning. A special SOI layer configuration suppressed dark current generation at the BOX interface. This prevents QE loss at short wavelengths, reduces cross-talk, and provides a low-resistance backplane. An imager-compatible bulk-CMOS process was then used for fabrication. Before thinning, a handle wafer offering mechanical support was bonded to the processed wafer using a low temperature oxide-oxide process.

We connected the front-side metals to the bond pads on the (exposed) backside using tungsten-filled and liner-oxide-isolated through-silicon vias (TSVs). However, we did not use “3D” stacked technologies such as multi-wafer vias or bonding of multiple wafers with sub-micron alignment. This significantly enhanced manufacturability.

Next, we used backgrind to remove most of the silicon, followed by a dry silicon etch. This wafer-level thinning produced a thinned monolithic imager with a planar back surface, which is important for subsequent color filter and microlens processing. The processing finished with the connection of the backside bond pads to the TSVs, standard oxide/nitride passivation, and hydrogen anneal. We did not apply any special anti-reflective coating. The die assembly used a simple wire-bonded package, which is similar to that used in an FSI part.

Clear advantages

As seen in the table, the BSI approach has a clear advantage over FSI in key areas. On a black and white sensor, the broadband QE (81% for BSI) was 2.7x better than FSI. Other parameters were comparable to or better than FSI. The fact that the mean dark current value and the hot pixel counts were similar for BSI and FSI indicates that we achieved a high-quality back interface without any post-thinning backside treatment.

Our results showed that a BSI sensor can capture a bright image using just one third of the light required by an FSI sensor. In practical terms, with BSI those birthday cake-and-candle pictures should have a much better chance of turning out – even when the lights are dimmed.

The effective optical stack height, which is the distance between the microlens and the absorbing silicon layer, is much smaller in the case of BSI. The dotted line shows where photon absorption begins. (Dimensions are in microns)

Tom Joy has worked in the CMOS industry for over twenty-eight years, including Hewlett Packard, Chartered Semiconductor, Agilent Technologies and Magnachip Semiconductor. For the last four years, he has been workinng on image sensor process development, and most recently on SOI based back illuminated sensors. He has a Ph.D. EE from the University of Notre Dame.