The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.
First, let’s consider the markets we’re addressing.
The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.
Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.
It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.
The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.
FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.
FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.
In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.
The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.
The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.
This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.
With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.
FD-SOI: Competitive Positioning
To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.
Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)
Gate cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)
The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.
Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.
The gate cost of 20nm FD-SOI is 20% lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.
14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.
Why the hesitation in using FD-SOI?
While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.
Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.
FD-SOI for High-Volume Applications
The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).
To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:
At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.
The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.
By Jean-Eric Michallet, Hughes Metras and Perrine Batude (CEA-Leti)
The miniaturization of the MOSFET transistor has been the main booster for the semiconductor industry’s rapid growth in the last four decades. Following “Moore’s Law”, this scaling race has enabled performance increases in integrated circuits at a continuous cost reduction: today’s $200 mobile phone has as much calculating power as multi-million-dollar supercomputer 10 years ago! But at 28nm, it seems the race is over: Moore’s scaling is facing obstacles – parasitic phenomena, incompressible delays, energy dissipation – that can be overcome with technology, but not in a way that is economically sustainable for everyone. This is where the idea to go 3D comes in: the density and cost dictated by Moore’s Law would be achieved not by 2D shrinking but by going up into the third dimension.
Piling transistors on top of each other in a “3D” configuration is not new. Stacking techniques using through-silicon vias (TSVs) are currently used for CMOS image sensors, MEMS, and now 3DNAND. In these scenarios, the devices themselves are processed on separate wafers, then aligned and bonded. The TSVs are essentially copper columns added to connect the top and bottom devices. While beneficial in certain cases, the TSV approach faces its own set of challenges with respect to aligning the transistors, the comparatively wide diameters of the TSVs, the pitch and the overall thickness.
Monolithic 3D (M3D), which takes a very different approach to stacking transistors on top of each other, is one of the most promising alternatives approaches when going 3D. M3D aims at increasing transistor density “sequentially” – meaning within a single process flow, as opposed to the TSV approach, which is applied to die that have already been processed. Staying within the bounds of a single process flow makes M3D much more cost-effective. M3D will enable an increased density of transistors without requiring the downscaling of their individual features. M3D could also provide a gain in performance by reducing the metal wiring delay, thanks to direct contact between transistor levels. From a cost perspective, M3D appears to offer a competitive advantage over equivalent N+1 scaling nodes: the scaling achieved in node N and even N-1 can be leveraged for another generation.
At CEA-Leti in Grenoble (France), one of the world’s most advanced microelectronics R&D centers, CMOS-device teams are exploring various routes to meet increased performance requirements of future semiconductor applications. M3D is a primary focus in the search for alternate routes to scaling, in addition to other disruptive approaches such as steep slope devices, mechanical switches based on NEMS and single electron transistors.
Leti is known for its expertise in the fields needed to demonstrate and take the industry lead in the M3D concept:
Leti’s M3D program was first launched in 2007. In order to reach the expected performance with an acceptable time to market, M3D must be developed with close, simultaneous attention to applications, design and technology challenges. The success demonstrated since the program launch prompted Qualcomm to partner with Leti in 2014 to explore M3D technology potential for future generations of products.
Leti’s M3D: How it’s done
The M3D concept consists of sequentially processing:
Using an SOI wafer for the top layer molecular bonding provides higher crystalline quality, greater integration density, and accurate thickness control. CEA-Leti has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.
The main advantages of M3D are derived from the sequential fabrication of the various transistor layers on the same wafer. It leads to very high alignment accuracy (3D contact pitch <100nm using lithography tools adapted to 14nm production), uses high-density interconnects, and surpasses 3D-TSV performance at a competitive cost. The inter-metal levels also facilitate design partitioning and architecture exploration.
Leti’s M3D approach is of particularly high value for those products that do not really benefit from scaling, especially when cost constraints are stringent. Different design simulations estimate a gain of one-node performance without scaling constraints. Once the remaining challenges are overcome, potential applications range from heterogeneous stacks (imagers, MEMS on logic) to advanced memory structures, advanced processors, programmable logic and various SOCs. All those products would benefit greatly from the added value provided by M3D:
PDK & Model Availability
In addition to the M3D technology process flow development, CEA-Leti is also proposing a Predictive Design Kit (PDK) that provides a primitive M3D product design environment for integrated modeling, simulation, visualization and communication. It also includes validation tools that product designers need to benchmark M3D and explore new architecture concepts. The first M3D PDK version available from CEA-Leti will permit partners to get a first knowledge of the M3D technology, so they can run initial performance assessments regarding density, speed, power and cost.
Part of CEA-Leti’s mission is to develop technologies that are ready to transfer to industry, supporting customers in both developing knowledge and implementation on the manufacturing floor. In the case of M3D, CEA-Leti is beginning to build a full ecosystem of partners to enable the rapid industrialization of this technology. Qualcomm, a world leader in wireless technologies, joined CEA-Leti in its M3D R&D program in 2014 and has committed resources to assess the feasibility of the concept.
To expand the momentum around M3D, while validating design-and-process assumptions and expected performance through prototyping demonstrators, the ecosystem should also involve a major foundry. CEA-Leti also plans to include additional members of the semiconductor business value chain (device modeling, EDA, process tooling, test, etc.) to form a complete M3D ecosystem, and make M3D a competitive technology for industrial transfer.
In the short term, CEA-Leti is looking for interested companies to engage in an R&D program aimed at validating proof of concept of an M3D integration process flow and its related libraries for advanced CMOS nodes.
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This SOI-based process requires no post-thinning passivation step.
Demand for better cameras in less expensive mobile phones is pushing researchers to find higher performance image sensor solutions for that cost-conscious end of the market. Last year, a research team from MagnaChip and JPL presented a paper at the International Electron Devices Meeting (IEDM 2007, Washington, DC) demonstrating the development of a production-worthy, backside-illuminated (BSI) monolithic sensor with 2.2 µm pixels. We used low-cost, standard fabrication techniques and available, mature technology modules. Compared to a conventional, frontside-illuminated (FSI) sensor, our 2-megapixel (MP) sensor exhibited comparable dark current and noise, but much higher quantum efficiency (QE) and sensitivity.
As shown in the figure, the height of the optical stack is much lower for the BSI pixel, leading to significant advantages in the effective pixel f/ (effective focal length) number. Furthermore, thanks to the high refractive index of silicon, light converges at the center of the pixel, and the optical energy is well-contained therein.
We began the fabrication process with SOI wafers, which enables the oxide to act as an etch-stop for accurate backside thinning. A special SOI layer configuration suppressed dark current generation at the BOX interface. This prevents QE loss at short wavelengths, reduces cross-talk, and provides a low-resistance backplane. An imager-compatible bulk-CMOS process was then used for fabrication. Before thinning, a handle wafer offering mechanical support was bonded to the processed wafer using a low temperature oxide-oxide process.
We connected the front-side metals to the bond pads on the (exposed) backside using tungsten-filled and liner-oxide-isolated through-silicon vias (TSVs). However, we did not use “3D” stacked technologies such as multi-wafer vias or bonding of multiple wafers with sub-micron alignment. This significantly enhanced manufacturability.
Next, we used backgrind to remove most of the silicon, followed by a dry silicon etch. This wafer-level thinning produced a thinned monolithic imager with a planar back surface, which is important for subsequent color filter and microlens processing. The processing finished with the connection of the backside bond pads to the TSVs, standard oxide/nitride passivation, and hydrogen anneal. We did not apply any special anti-reflective coating. The die assembly used a simple wire-bonded package, which is similar to that used in an FSI part.
As seen in the table, the BSI approach has a clear advantage over FSI in key areas. On a black and white sensor, the broadband QE (81% for BSI) was 2.7x better than FSI. Other parameters were comparable to or better than FSI. The fact that the mean dark current value and the hot pixel counts were similar for BSI and FSI indicates that we achieved a high-quality back interface without any post-thinning backside treatment.
Our results showed that a BSI sensor can capture a bright image using just one third of the light required by an FSI sensor. In practical terms, with BSI those birthday cake-and-candle pictures should have a much better chance of turning out – even when the lights are dimmed.
Tom Joy has worked in the CMOS industry for over twenty-eight years, including Hewlett Packard, Chartered Semiconductor, Agilent Technologies and Magnachip Semiconductor. For the last four years, he has been workinng on image sensor process development, and most recently on SOI based back illuminated sensors. He has a Ph.D. EE from the University of Notre Dame.