Tag Archive IMEC

ByAdele Hars

RFSOI Short Course – Great Line-Up! (EuroSOI, March 2018)

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.

The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.

The talks, which are being given by a stellar line-up of experts, include:

  • RF SOI, fabrication, materials and eco-system – Ionut Radu Director of Advanced R&D, Soitec
  • Fundamentals of RF SOI technology – Jean-Pierre Raskin, Professor, UCL
  • 22nm FDSOI Technology optimized for RF/mmWave Applications – David L. Harame, RF CTO Development and Enablement, GlobalFoundries
  • RF SOI technology and components for 5G connectivity – Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti
  • Analog and RF design on SOI – Barend van Liempd, Senior Researcher, imec
  • Techniques and tricks for RF measurements on SOI – Andrej Rumiantsev, Director RF Technologies, MPI Corporation
  • FOSS TCAD/EDA tools for advanced SOI-device modeling – Wladek Grabinski, R&D CM Manager, MOS-AK
  • RF design flow for SOI – Ian Dennison, Design Systems Senior Group Director, Cadence

The course is being organized by SOI Consortium members Incize and Soitec.

BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs.

EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.

 

 

 

ByAdministrator

RF-SOI: Already in Every Smartphone, New Opps Abound in IoT (SF Workshop Part 3 of 3: IBM, ST, GF and more)

RF-SOI is already found in virtually every new smartphone out there, so the RF-SOI session of the recent FD-SOI/RF-SOI Workshop in San Francisco focused on long-term growth and further opportunities.

In case you missed it, ASN already covered the SF Workshop’s FD-SOI presentations (Samsung, ST and the EDA houses – click here for that post) and the panel discussion (where we learned Cisco is working on an FD-SOI chip – click here to read that post). As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience.

The presentations are becoming available on the SOI Consortium website, so keep checking there. (Also, if you want to know more about how the special wafers for RF-SOI solve design challenges, Soitec contributed an excellent ASN article a couple years ago – click here to read it.) But for now, here’s a brief recap of the RF-SOI presentations.

IBM

IBM has been offering RF-SOI foundry services since 2007 and recently said it shipped more than 7 billion RF-SOI chips in the last 3 years (read more about that here). Clearly they are experts in this business. In his talk, RF-SOI: Redefining Mobility and More in the Front-End, Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group, said that LTE is the fastest developing mobile system technology ever. A big driver is mobile video: the CAGR there is 66% over the next five years, and it’s happening on both high-end and low-end smartphones.

IBM_RFSOI_LTE

 

Next comes IoT as an RF-SOI driver, and he gave a roadmap and examples.

IBM_RFSOI_IoT

He also looked at demand for RF-SOI wafers, which are typically 200mm, but he noted that 300mm is starting to sustain growth, too.

IBM_RFSOI_wafers_lowres

(You might also want to also refer to the IBM RF-SOI presentations given recently in Shanghai and Tokyo.)

ST

In her presentation entitled, ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics focused on front-end module (FEM) integration (ST contributed an excellent article on this to ASN last summer – you can read it here). She made the link between new opportunities in RF-SOI and new developments by Soitec in RF-SOI wafers.

ST_RFSOI_roadmap

Putting power amplifiers (PA) on RF-SOI is starting to happen, and she provided data showing that they’re now closing in on GaAs in terms of performance.

ST_RFSOI_PA

ST is offering H9SOI_FEM on a foundry basis and as a partner. They can deliver prototypes within three weeks, and provide full integration up to packaging. (While you’re waiting for this presentation to be posted on the SOI Consortium website, you might want to refer to a similar presentation given recently by ST in Tokyo.)

GlobalFoundries

In SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, Director of RF Segment Marketing at GlobalFoundries, focused on the value of SOI in RF, and explained why it presents an important opportunity for innovation at the system level.

GF_RFSOI_why

GF is the foundry partner for Peregrine (now part of Murata), and he showed how the GlobalONE PA integration is an excellent example of innovation opportunities.

GF_RFSOI_Peregrine

With an example of tunable filters, he also posited that the combination of FD-SOI and RF-SOI is a way to create disruption in wireless markets.

GF_RFSOI_FDSOI_filters

 

Incize

Incize is a spin-off of UCL in Belgium, which is a powerhouse in RF characterization. In fact, Soitec’s trap-rich SOI wafers, which are now being commercialized under the eSI moniker and launching a veritable RF revolution, were developed in partnership with UCL (you can read about that here). In his presentation entitled RF SOI: from Material to ICs – an Innovative Characterization Approach, Incize CEO Mostafa Emam explained non-destructive characterization for RF. Incize is currently working with eight customers, including wafer manufacturers. He highlighted the value of RF-SOI, and showed the characterization of Trap Rich vs. previous generations of high-resistivity (HR) SOI.

Imec

Barend Van Liempd, PhD Researcher at IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,) gave a talk entitled Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers. (He also presented this in a paper at ISSCC a few days prior.) He covered a highly integrated FEM program at Imec based on IBM technology and Electrical-Balance Duplexers.

More Workshops Coming

If you’d like to learn more about RF-SOI and/or FD-SOI, members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events throughout the coming year, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

ByAdministrator

Top Silicon Valley Companies Signed Up for FD-SOI & RF-SOI Forum (27 Feb. 2015 in SF, free, registration still open)

Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.

FDSOI_SF15_workshopIf you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.

Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.

Morning session: FD-SOI Workshop

FD-SOI foundry offer

  • FD-SOI Advantages for Applications and Ecosystem — Philippe Magarshack, CTO, STMicroelectronics
  • 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm — Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI
  • [Title TBA] — Jamie Schaeffer, GlobalFoundries

FD-SOI IP offer

  • Synopsys FD-SOI IP Solutions — Mike McAweeney, Sr. Director IP Product Sales, Synopsys
  • FD-SOI: Ecosystem and IP Design — Amir Bar-Niv, Senior Group Director, Product Management, Design IP, Cadence

FD-SOI design experience

  • [Title TBA] — N. Ben-Hamida, High speed Analog Design Manager, Ciena
  • 28nm FD-SOI Design/IP Infrastructure — Shirley Jin, Sr. Director of Engineering, Verisilicon

Panel discussion

Advantages and opportunities when designing with FD-SOIModerator: Dan Nenni, SemiWiki

Panelists:

  • Marco Brambilla, Director of Engineering, Synapse
  • Wayne Dai, Chairman, President & CEO, VeriSilicon
  • Kelvin Low, Sr Director, Foundry Marketing, Samsung SSI
  • Philippe Magarshack, CTO, STMicroelectronics
  • Guntram Wolski, Cisco Systems

Innovation

  • Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator — Mike Noonen, Chairman & Co-founder, Silicon Catalyst

Afternoon session: More than Moore Forum

  • RFSOI: Redefining Mobility and More in the Front-End – Mark Ireland, VP of Strategy and Business Development, Microelectronics Division, IBM Systems & Technology Group
  • Towards a Highly-Integrated Front-End Module in RF-SOI Using Electrical-Balance Duplexers — Barend Van Liempd, PhD Researcher, IMEC (Perceptive Systems dept.) / Leuven & Vrije Universiteit Brussel (VUB) (ETRO dept.,)
  • RF SOI: from Material to ICs – an Innovative Characterization Approach — Mostafa Emam, CEO, Incize
  • ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration — Laura Formenti, Infrastructure and RF-SOI BU Director, STMicroelectronics

If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.

This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.

For the SF event – here’s the key information:

FD-SOI and RF-SOI Forum

  • Friday, February 27th, 2015, 8am to 6pm
  • Palace Hotel
  • 2 New Montgomery Street, San Francisco, California, 94105 (USA)

The event is free but pre-registration is mandatory – click here to sign up on the SOI Consortium website.

ByAdministrator

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

(Image courtesy: SEMI)

 

For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.

And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.

So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.

Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.

For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.

In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.

 

FD-SOI at the Semicon Europa Low Power Conference

The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conferencewhich features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.

Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.

Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.

Other talks include imec on FinFETs, Imagination Technology on MIPS, Qualcomm on the “Landscape for More Moore”, and Leti on FD-SOI and 3D stacking for multicore embedded systems.

Renesas will detail their flavor of FD-SOI, which they’ve been working on for a long time (especially with innovations from Hitachi). They call it Silicon-on-Thin-Buried Oxide, aka SOTB.

David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)

Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.

Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)

The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).

ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.

 

Power and 3DI

A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.

Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.

Hope to see you in Grenoble!

ByGianni PRATA

imec 28 Gb/s photonics platform in upcoming multiproject SOI wafer runs

imec’s 28Gb/s silicon photonics platform for optical interconnects and other optical applications will be included in an upcoming multiproject wafer run, reports R. Colin Johnson in EETimes (read the article here). These runs, which are on SOI wafers, are a joint effort by ePIXfab (founded by imec and Leti), Europractice IC and MOSIS.  They provide a cost-effective vehicle for fabless researchers in data and telecom.

ByAdministrator

SOI: Looking Back Over a Year of Moving Forward (Part 1, FD-SOI)

2014’s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise.

But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year.  In fact, there was so much happening that we’ll review 2013 in two posts – this post is about FD-SOI; in the next post we’ll cover RF-SOI and FinFETs.

Highs, lows, and the promise of an extra day

It was just a year ago that you read in the first ASN post of 2013 about ST-Ericsson’s NovaThor™ L8580 ModAp: at 2.5GHz it was “the world’s fastest and lowest-power integrated LTE smartphone platform” at CES ’13 in Las Vegas.  Then in February in Barcelona ST announced that its 28nm FD-SOI technology clocked in at 3GHz, but what was really amazing was that it got 1GHz using using just 0.6V VDD, aka the “supply voltage”, which is the main voltage “in” that powers the chip. No one had been able to run stably on that low a voltage before.  28nm FD-SOI got you a full extra day before you had to recharge your device.

But then of course came the sad news that the plug was pulled on ST-E. Happily the technology moved into the ST fold, and the 28nm process is now ramping in volume, with 14nm is set to debut shortly.

 

ST300mmFDSOIwaferMay was a big month. ST’s FD-SOI got the EETimes ACE Award for Energy Technology – and the company announced it had started winning FD-SOI customers. We also got the news of a big public-private funding boost, to the tune of €360M, for the Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe). It is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL. A 3-year public-private project involving 500 engineers from 19 members in seven countries, it’s looking to enable volume manufacturing in Europe from 28nm down to 10nm.

Also in May, Leti told us that they’d gotten silicon layers down to 3.5nm, and for boosting pFETs with SiGe, were seeing better results with FD-SOI than bulk FinFETs. What’s more, they found that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!

In August, the French government upped the ante with a 600 million Euro investment in the Nano2017 program, which was in addition to the 3.5 billion Euros that ST and partners had already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).

In October, Leti said it would have the 10nm FD-SOI PDK ready in June of 2014.

In November, the wafer supply chain got a boost when SOI wafer suppliers Soitec and SunEdison (formerly MEMC) ended their longstanding legal feud and entered into a patent cross-license agreement.

At IEDM in December Leti announced UTSOI2, a compact model for electrical simulations. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers use before they run silicon. Dedicated to Ultra-Thin Body and Box (UTBB) FD-SOI technology, UTSOI2 accurately describes independent double gate operation for sub-20nm nodes. Also at IEDM, ST, Leti, IBM, Renesas, Soitec and GlobalFoundries presented the big paper showing great results for 14nm FD-SOI.

So 2014 promises to be an excellent year.  Stayed tuned – next up we’ll review the great strides made in RF-SOI and SOI-FinFETs.

From all of us here at ASN, wishing you a safe, happy, healthy, prosperous and innovative New Year!

ByGianni PRATA

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs.

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS’ customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology. Co-founded by Leti and imec in 2009, ePIXfab offers a cost-effective way for researchers and small and medium sized companies to prototype photonic integrated circuits on SOI.

ByGianni PRATA

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.”

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving  the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

IEEE Division I Director, Cor Claeys (right) of imec, honoring Dr. Jean-Pierre Colinge (left) of TSMC for receiving
the 2012 Andrew S. Grove Award for his contributions to SOI. The presentation was made during the 2012 ESSDERC meeting in Bordeaux, France. (Photo Credit: Yann Deval, ESSDERC-ESSCIRC Conference Chair)

Dr. Jean-Pierre Colinge received the 2012 IEEE Andrew S. Grove award at the last ESSDERC-ESSCIRC Conference, for his “contributions to silicon-on-insulator devices and technology.” One of the industry’s most prestigious, the Grove Award is sponsored by the IEEE Electron Devices Society, recognizing “outstanding contributions to solid-state devices and technology.” As noted in the EDS Newsletter, Dr. Colinge’s “…strong actions and enthusiastic beliefs were crucial for supporting the development of SOI technology.” One of the giants of the SOI community, Dr. Colinge is especially heralded in the industry for his seminal and continued work in multigate FETS (aka MuGFETs, a category that includes architectures such as FinFET and TriGate among others). Dr. Colinge and his work have been featured in many editions of ASN. Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari  (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).

ByGianni PRATA

The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost.

The FD-SOI design and manufacturing ecosystem has just gotten a €360M boost. A new 3-year public-private project involving 500 engineers from 19 members in seven countries is looking to enable volume manufacturing in Europe from 28nm down to 10nm. The Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL.

ByGianni PRATA

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

Meritage Resort and Spa in Napa Valley

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)

The papers

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. FullyDepleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: FullyDepleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

The courses & panel

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?