Tag Archive IoT

ByGianni PRATA

MegaChips Buys SOI-MEMS Timing Leader SiTime

SOI-MEMS timing device leader SiTime Corporation is being acquired by MegaChips Corporation, a top 25 fabless semiconductor company based in Japan for $200 million in cash. (read the press release here). This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.

“MEMS components are fuelling the growth of the semiconductor industry, “said Akira Takata, President and CEO of MegaChips Corporation.  “Through the acquisition of SiTime, MegaChips becomes a leader in MEMS. SiTime will help us expand our portfolio and diversify our customer base.  SiTime technology is the perfect match for MegaChips’ solutions that target Wearables, Mobile and IoT markets.”

SiTime’s innovative SOI-MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.  ASN has been following SiTime for over five years, since they first spun off of Bosch, and CTO Markus Lutz explained the role SOI plays in their technology (which you can read here). You can also read more about SiTime products and technology here by clicking the ASN SiTime tag.

SiTime will retain its name and operate as a wholly owned subsidiary of MegaChips.

 

ByAdministrator

Is China Interested in FD-SOI? You bet.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations.

The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM (see below for key slides and links to the full presentations). The goal was to gather IC industry decision makers, technology owners, opinion leaders and market analysts to exchange and assess the opportunities that FD-SOI technology brings in terms of ultra-low power operation at high performance for mobile and IoT.

 

A panel discussion during the SOI Consortium's Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

A panel discussion during the SOI Consortium’s Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

Here are some of the points made by the speakers:

  • FinFET is a tough (Intel is running 15 months behind) and capex consuming technology (exponential situation in terms of costs), so not everybody will be able to go for it
  • FD-SOI will be a game changer
  • the FD-SOI ecosystem is now ready but industry still seems a bit too conservative to get started
  • FD-SOI is a great opportunity for China to take the lead
  • need a big fabless house with a high-volume application and then foundries building capacity
  • promising outlook: designs are underway; in 6 to 9 months there could be significant volumes. It is no longer a question of why FD-SOI – now we are at when FD-SOI.
  • 28nm will be a long lifetime technology node (2012-2024)
  • IoT: a good opportunity for FD-SOI
  • work is being done by the ecosystem to improve FD-SOI IP
  • FD-SOI is not only for 28nm but also 20/22nm and 14nm (ST discussed its 14nm FD-SOI)
  • the industry acknowledges ST and Soitec’s commitment to developing FD-SOI technology

We know that FD-SOI 28nm has moved into the manufacturing and volume production phase. It offers the chip industry the unique features of being able to fabricate at competitive cost, ultra low power, high speed ICs. It is a game changer technology platform that brings new powerful elements to the designers and a strong differentiation potential at IC and system level. But the speakers acknowledged that challenges remain, in particular that there’s a need for a greater commitment from industry and for very big customers (but that’s going to change).

 

The presentations

Here are brief summaries of the presentations. Click on the presentation names to download the full pdfs, or on the slides for enlarged images.

Market Overview and Opportunities by Handel Jones, CEO, International Business Strategies

Starting from a bird’s-eye view of the world, this presentation then zooms down deep into the nitty-gritty of chip manufacturing costs. Considering the various technology options for current and future nodes, it looks at costs per gate and per wafer, costs for design and for tooling, yield impact and fab life. The world’s largest chip consumer, China currently imports about 90% of the chips used there. The government has targeted 2020 as the year by which Chinese semiconductor companies should be supplying 40% of semiconductors consumed in China. IBS sees FD-SOI as the most astute choice, especially for IoT.

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

 

FD-SOI Technology by Laurent Remont, VP Technology & Product Strategy, STMicroelectronics

This presentation gives an overview of FD-SOI technology, roadmaps and markets. One of the points made is that 28nm will be the longest process generation with the highest volume manufacturing. FD-SOI extends the 28nm offering with improved power and performance rivaling existing 20nm bulk.

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

 

Design with FD-SOI, Innovation Through Collaboration by Marco Casale-Rossi, Product Marketing Manager, Synopsys

The Synopsys presentation detailed FD-SOI/EDA readiness, with illustrations from an ST design. Among the many impressive results, time-to-good-floorplan was reduced 10x, and leakage was reduced by 59% through advanced EDA in the flow.

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

 

Designing with FD-SOI for Power Efficiency by Haoran Wang, Associate General Manager, Synapse Design China

Synapse Design is an industry leader in design services for most top tier semiconductor and system companies around the world. They have been working on designs in FD-SOI for over four years. In fact, they’ve already had four tapeouts in FD-SOI and are working on three others. The presentation noted that “…FD-SOI has more degrees of freedom than bulk” conferred by device physics. They recommend starting with a deep power analysis at RTL, looking carefully at performance requirements vs. battery life. They conclude, “At 28nm, FDSOI does show the benefits of speed/power advantage. It is a viable solution from technology point of view and easy to be integrated in current design flow.”

 

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

 

Leveraging FD-SOI to Achieve Both Low Power AND High Speed by Pete Fowley, CEO, Wave Semiconductors

Wave is a fabless semiconductor startup “commercializing a programmable solution addressing power, concurrency, design time, design cost, and deep submicron challenges facing the semiconductor market.” The founders come from a veritable who’s who industry background* (the CEO was one of the first members of Apple’s original Mac chip design team). They bill their FD-SOI based Wave Threshold Logic (WTL) as their “secret sauce”. WTL can use both very fast flip-well LVT devices with Forward Body Bias (FBB) and Standard VT devices that have very low leakage through very high Reverse Body Bias (RBB). According to Wave, “WTL‐ BB represents a unique differentiator for FD‐SOI: enabling significant performance and power advantages over bulk processes. This strategic advantage will persist into deeper nodes.” Clearly one to watch!

 

The FD-SOI Technology for Energy Efficient SoCs by Giorgio Cesana, Director of Marketing, STMicroelectronics

Here ST gives a FD-SOI primer, explaining the technology, design considerations and Forward Body Bias (FBB) use and results. Examples from both fast CPU/GPU and ultra-low power designs are given.

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

SOI Ecosystem – Strategic Opportunity for China by Tom Reeves, VP Technology Alliance, IBM

The SOI ecosystem is a central theme in this presentation. It has a long history of producing successful ICs, and the SOI enabled device structure pipeline continues through 7nm. IBM sees big opportunities for China in mobile, automotive, industrial, IoT, wearable and other More-than-Moore apps. The call to action is clear: now is the time for China to accelerate the building of its SOI ecosystem.

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Foundry Business Opportunities by Paul Colestock, Sr. Director of Segment Marketing, GlobalFoundries has not yet been posted as of this writing. But keep checking back – it should be there soon.

Also, look for another ASN post on the Shanghai 2014 RF-SOI Workshop coming up shortly.

~~

Special thanks to the folks at the SOI Consortium for their help in compiling details for this piece.

* A tip of the hat to Eric Esteve at Semiwiki for first pointing this out in his recent piece on Wave Semi’s technology, which you can read here.

ByAdministrator

FD-SOI Front and Center at Very Successful Semicon Europa

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).

This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported.  Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.

 Low Power Conference

It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go.  He indicates a major announcement is impending.

 

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk  — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality.  He sees it having a very long life, with monolithic 3D stacking replacing scaling.

The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.

Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers.  His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Shiro Kamohara, Chief Engineer of the Low Power  Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT.  They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share.  For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.

A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said.  He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.

Power (high & smart), power (very low), 3D and more

During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”.  While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%.  Look for more breakthroughs in their paper at IEDM this December, she said.

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)

ST’s FD-SOI demo (Semicon Europa 2014)

ST’s FD-SOI demo (Semicon Europa 2014)

So it was a great show – kudos to the folks at Semi.  Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.

 

ByGianni PRATA

More FD-SOI myth-busting, courtesy semiwiki

In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI.  He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.

ByGianni PRATA

Engaging Kleinman (ex-GF/Xilinx) piece on LinkedIn Advocates for 28nm FD-SOI

A thoroughly engaging and amusing LinkedIn Pulse piece by Bruce Kleinman comes down firmly on the side of 28nm FD-SOI.  Entitled 28nm: Home Improvements (posted 13 August 2014), it’s subtitled, “Welcome to 28nm! Make yourself comfortable, we’re going to be here for awhile.” He says (among lots of other things, including astute observations about 3D), “…in my book 28nm FD-SOI offers very similar performance/power characteristics to 20nm bulk silicon.” Kleinman’s currently SVP at HMicro, which is doing SOC solutions for demanding wireless apps and IoT.  He’s clearly got the street creds, arriving there by way of upper management at GlobalFoundries, Xilinx, HP, etc., having started out with a Stanford MSEE.  A good read – recommended.

ByAdministrator

The SOI Papers at VLSI ’14 (Part 2):

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!

 

(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.

 

4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.

 

6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.

 

8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalon et al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.

 

9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.

 

13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

 

13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

 

17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

 

18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.

 

18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.

 

18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.

 

SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.

 

UTwenteC194VLSI14lowres

(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)

 

 

C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

ByGianni PRATA

IBM Specialty Foundry Shipped Over 7 Billion RF-SOI Chips in Last 3 Years, Launches New RF-SOI Technology

7SW SOI-lightningbolt_060314final

 

IBM Foundry Solutions announced a new SOI-based technology for RF called 7SW SOI. The company says it is designed for 30 percent better performance than its predecessor, 7RF SOI, with which IBM shipped over seven billion chips in the last three years. The new mobile phone chip technology can help device manufacturers provide consumers with extremely fast downloads, higher quality connections, and longer battery life than its highly successful predecessor, says an IBM spokesperson. The new technology is designed to take advantage of more frequency bands, taking phone manufacturers one step closer to the reality of creating a “world phone” that can be used anywhere.

 

 

 

 

Here are the key points:

  • The new technology gives designers added flexibility, enabling them to develop chips that integrate more function or that take up to 30 percent less space, depending on design goals.
  • The new technology is a hybrid 180nm/130nm technology base and devices optimized to accommodate aggressive LTE standards and demanding worldwide coverage requirements
  • It is optimized for multi-band switching in next-generation smartphones.
  • Poised to drive innovation in newer category of smart devices in the Internet of Things as the new technology is an ideal fit for high-band LTE and Wi-Fi 5.8 GHz band applications.
  • Clients can exploit the technology advances offered by 7SW to develop solutions that enhance user experiences, including broader geographic mobility and faster data rates for high definition video.

For a helpful brochure on IBM’s RF foundry offerings, click here.

ByAdministrator

Interview: Leti CEO Malier on the FD-SOI Breakthrough; Leti Days in Grenoble (24-26 June) & Semicon West

Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM.  Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.

To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.

ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news.  (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).

LaurentMalierLeti

Laurent Malier, CEO of CEA-Leti

Here are some excerpts from our conversation.

Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?

Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost.  In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology

 

ASN: In which areas did Leti contribute to FD-SOI development?

LM:  Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention.  Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.

Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.

 

ASN: Do you see opportunities for FD-SOI in IoT?

LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data.  You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise.  Look for more announcements coming up at Leti Days.

LetiDays2014

ByGianni PRATA

SiTime Enters Wearables, IoT Markets with 32 kHz SOI-MEMS

SiTime--SiT1552-TCXO-PR-Graphic-med

(Courtesy: SiTime)

SiTime, which leverages SOI for high-performance MEMS timing solutions, has introduced what it says is the smallest, lowest power 32 kHz TCXO (temperature compensated oscillator – read the press release here). With its tiny footprint and ultra-low power consumption, the SiT1552 MEMS TCXO enables a paradigm shift in the size and battery life of wearable electronics and Internet of Things (IoT); such benefits are not available from legacy quartz devices.

“The SiT1552 MEMS TCXO is 20% of the size and consumes 50% of the power of comparable quartz devices,” said Piyush Sevalia, executive vice president of marketing at SiTime. “Our MEMS enable new system architectures that offer higher performance, small size and longer battery life. With another industry first, we continue to revolutionize the timing industry with our breakthrough MEMS solutions.”

SiTime’s posted a helpful video that details the features of the SiT 1552 – click here to view it. There’s also a FAQ and a ppt presentation.

Devices are  in production now. Pricing is available upon request.