Tag Archive IP

ByAdele Hars

Synopsys IP for 22FDX Automotive – Why It Matters (Courtesy: D. Nenni, semiwiki)

Daniel Nenni, CEO & Founder, SemiWiki.com

Note to our readers: Semiwiki Founder Dan Nenni recently wrote an excellent piece on the importance of the Synopsys investment in automotive IP for GlobalFoundries’ 22FDX (FD-SOI) technology. He graciously has given us permission to reprint it here in ASN.

By Dan Nenni, CEO & Founder, SemiWiki.com

IP vendors have always had the inside track on the status of new process nodes and what customers are planning for their next designs. This is even more apparent now that systems companies are successfully doing their own chips by leveraging the massive amounts of commercial IP available today. Proving once again that IP really is the foundation of modern semiconductor design.

Automotive is one of those market segments where systems companies are doing their own chips. We see this first hand on SemiWiki as we track automotive related blogs and the domains that read them. To date we have published 354 automotive blogs that have been viewed close to 1.5M times by more than 1k different domains.

(Courtesy: semiwiki.com and GlobalFoundries)

The recent press release by Synopsys and GLOBALFOUNDRIES didn’t get the coverage it deserved in my opinion and the coverage it got clearly missed the point. Synopsys, being the #1 EDA and #1 IP provider, has the semiconductor inside track like no other. For Synopsys to make such a big investment in FD-SOI (GF FDX) for automotive grade 1 IP is a huge testament to both the technology and the market segment, absolutely.

I talked to John Koeter, Vice President of Marketing for IP, Services and System Level Solutions. John is a friend and one of the IP experts I trust. 3 years ago Synopsys got into automotive grade IP and racked up 25 different customer engagements just last year. The aftermarket electronics for adding intelligence (autonomous-like capabilities, cameras, lane and collision detection, etc…) to older vehicles is also heating up, especially in China.

I also talked to Mark Granger, Vice President of Automotive Product Line Management at GLOBALFOUNDRIES. Mark has been at GF for two years, prior to that he was with NVIDIA working on autonomous chips with deep learning and artificial intelligence. According to Mark, GF’s automotive experience started with the Singapore fabs acquired from Chartered in 2010. The next generation automotive chips will come from the Dresden FDX fabs which are right next door to the German automakers including my favorite, Porsche.

One thing we talked about is the topology of the automotive silicon inside a car and the difference between central processing and edge chips. Remember, some of these chips will be on glass or mirrors or inside your powertrain. The edge chips are much more sensitive to power and cost so FDX is a great fit.

Mark provided a GF link for more information:

Here is the link to our Automotive resources:
https://www.globalfoundries.com/mark…ons/automotive

One thing Mark, John, and I agree on is that truly autonomous cars for the masses is still a ways out but we as an industry are working very hard to get there, absolutely.

Here is the press release:

Synopsys and GLOBALFOUNDRIES Collaborate to Develop Industry’s First Automotive Grade 1 IP for 22FDX Process

Synopsys’ Portfolio of DesignWare Foundation, Analog, and Interface IP Accelerate ISO 26262 Qualification for ADAS, Powertrain, 5G, and Radar Automotive SoCs

MOUNTAIN VIEW, Calif., and SANTA CLARA, Calif., Feb. 21, 2019 /PRNewswire/ —
Highlights:

  • Synopsys DesignWare IP for automotive Grade 1 and Grade 2 temperature operation on GLOBALFOUNDRIES 22FDX®process includes Logic Libraries, Embedded Memories, Data Converters, LPDDR4, PCI Express 3.1, USB 2.0/3.1, and MIPI D-PHY IP
  • Synopsys’ IP solutions implement additional automotive-grade design rules for the 22FDX process to meet reliability and 15-year automotive operation requirements
  • Synopsys’ IP that supports AEC-Q100 temperature grades and ISO 26262 ASIL Readiness accelerates SoC reliability and functional safety assessments
  • Join Synopsys and GLOBALFOUNDRIES at Mobile World Congress in Barcelona, Spain on Feb. 25 for a panel on “Intelligent Connectivity for a Data-Driven Future”

Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES (GF) today announced a collaboration to develop a portfolio of automotive Grade 1 temperature (-40ºC to +150ºC junction) DesignWare® Foundation, Analog, and Interface IP for the GF 22-nanometer (nm) Fully-Depleted Silicon-On-Insulator (22FDX®) process. By providing IP that is designed for high-temperature operation on 22FDX, Synopsys enables designers to reduce their design effort and accelerate AEC-Q100 qualification of system-on-chips (SoCs) for automotive applications such as eMobility, 5G connectivity, advanced driver assistance systems (ADAS), and infotainment. The Synopsys DesignWare IP implements additional automotive design rules for the GF 22FDX process to meet stringent reliability and operation requirements. This latest collaboration complements Synopsys’ broad portfolio of automotive-grade IP that provides ISO 26262 ASIL B Ready or ASIL D Ready certification, AEC-Q100 testing, and quality management.

“Arbe’s ultra-high-resolution radar is leveraging this cutting-edge technology that enabled us to create a unique radar solution and provide the missing link for autonomous vehicles and safe driver assistance,” said Avi Bauer, vice president of R&D at Arbe. “We need to work with leading companies who can support our technology innovation. GF’s 22FDX technology, with Synopsys automotive-grade DesignWare IP, will help us meet automotive reliability and operation requirements and is critical to our success.”

“GF’s close, collaborative relationships with leading automotive suppliers and ecosystem partners such as Synopsys have enabled advanced process technology solutions for a broad range of driving system applications,” said Mark Ireland, vice president of ecosystem partnerships at GF. “The combination of our 22FDX process with Synopsys’ DesignWare IP enables our mutual customers to speed the development and certification of their automotive SoCs, while meeting their performance, power, and area targets.”

“Synopsys’ extensive investment in developing automotive-qualified IP for advanced processes, such as GF’s 22FDX, helps designers accelerate their SoC-level qualifications for functional safety, reliability, and automotive quality,” said John Koeter, vice president of marketing for IP at Synopsys. “Our close collaboration with GF mitigates risks for designers integrating DesignWare Foundation, Analog, and Interface IP into low-power, high-performance automotive SoCs on the 22FDX process.”

Resources
For more information on Synopsys DesignWare IP for automotive Grade 1 temperature operation on GF’s 22FDX process:

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About the Author

Daniel  Nenni has worked in Silicon Valley for over 35 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. He is the founder of SemiWiki.com (an open forum for semiconductor professionals) and the co-author and publisher of “Fabless: The Transformation of the Semiconductor Industry”, “Mobile Unleashed: The Origin and Evolution of ARM Processors in our Devices” and “Prototypical: The Emergence of Prototyping for SoC Design”.  He is an internationally recognized business development professional for companies involved with the fabless semiconductor ecosystem.

ByAdele Hars

GF-Dolphin 22FDX Turnkey Adaptive Body Bias Solutions Offer Big Energy Savings, Faster TTM. Design Kits Q2/19.

GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019.

As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.

The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.

“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”

“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”

As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of.

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*A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago:

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering’s Ann Steffora Mutschler from a couple years ago.

ByAdele Hars

New Bluetooth 5 RF IP from VeriSilicon Targets Wearables, IoT on GF’s 22FDX

Since about a third of all IoT devices are expected to be connected by Bluetooth, chip designers need IP solutions that will help reduce system cost and greatly improve battery life. And that’s just what VeriSilicon has announced for GlobalFoundries’ 22FDX® (FD-SOI) process.

“By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs,” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. 22FDX enables efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. GF and VeriSilicon are working on an SoC using VeriSilicon’s BLE 5.0 RF IP in GF’s 22FDX process.

The latest iteration of Bluetooth is 5, which (like its predecessor 4) has a Low Energy (LE) RF option – but with big improvements. According to the Bluetooth website, “With 4x range, 2x speed and 8x broadcasting message capacity, the enhancements of Bluetooth 5 focus on increasing the functionality of Bluetooth for the IoT.” BLE 5.0 was designed for very low power operation and is optimized for the sorts of short burst data transmissions you’ll get with IoT.

On the strength of VeriSilicon’s innovative RF architecture and by leveraging GF’s 22FDX technology, VeriSilicon says the new IP product achieves significant improvements in power, area, and cost compared to current offerings, so it will better serve the emerging and increasing wearable devices and IoT applications space.

“VeriSilicon’s BLE IP complements GF’s 22FDX FD-SOI capabilities and is well positioned to support the explosive growth of low-power IoT and connected devices,” said Mark Ireland, vice president of ecosystem partnerships at GF. “Together, we broaden our IP and services to further enable our mutual clients to provide power and cost efficient solutions.”

VeriSilicon BLE 5.0 RF IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management.

You can read the full press release in Chinese here and in English here.

ByAdele Hars

Chengdu Conference Indicates FD-SOI Will Play Major Role in China/Automotive

FD-SOI was a very important topic during the recent Mount Qingcheng China IC Ecosystem Forum. To situate things, Mount Qingcheng, with its lush hills and waterways, is located just outside of Chengdu. That of course is where GlobalFoundries is building its new fab, which will be the first in China to run FD-SOI. Chengdu is also a key city in China’s automotive electronics landscape.

(Image Courtesy: VeriSilicon)

The theme of the forum was Building a Smart Automotive Electronics Industry Chain. Over 260 decision-makers from government, academia and industry attended – and the SOI Consortium had a significant presence. The event was chaired by Wayne Dai, CEO/Founder of consortium member VeriSilicon, and tireless champion of the the FD-SOI ecosystem in China and worldwide. Morning keynotes were given by: Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Mark Granger, GF’s VP of Automotive Product Line Management; and Tony King-Smith, Executive Advisor at AImotive, a GF 22FDX customer.

BTW, transcripts of all the talks are available through Gasgoo, China’s largest automotive B2B marketplace. You can click here to access them. (They’re in Chinese – but you can open them in the language of your choice using the major translation websites.)

Chengdu Officials Affirm Support for FD-SOI

Fan Yi, Deputy Mayor of Chengdu, spoke extensively of FD-SOI in his keynote on the importance of rapidly developing smart cars.

He heralded the “spectacular” new GlobalFoundries fab there. Following a meeting with the company’s top brass the day before, he affirmed GF’s confidence in their investment. There is a solid roadmap for FD-SOI, he noted, and efforts are underway to accelerate the move into production and expand education and training. He cited the benefits of FD-SOI for the entire supply chain, from design through package and test, raising the level of the entire IC industry to new heights. The government, he said, attaches great importance to this enterprise. Their thinking regarding intelligent transport in China is integrated with the overall approach to smart cities.

SOI Consortium Leads Industry Keynotes

Wayne Dai, VeriSilicon Founder and CEO (Photo courtesy VeriSilicon)

In his opening remarks, Wayne Dai emphasized the need for China to seize the advantage in the next round of development opportunities in the automotive electronics industry. This year’s Qingcheng forum, he noted, brought together key representatives from across the supply chain, from of the highest to the deepest reaches of the smart car electronics industry, and across markets, technologies, solutions, industrial ecosystem, standards and regulations.

In his talk on how FD-SOI is boosting the accelerated development of automotive electronics, Carlos Mazure presented the SOI Industry Consortium. He noted that the Consortium promotes mutual understanding and development across the ecosystem. SOI is already present throughout automotive applications, he noted. There are currently about 100mm2 of SOI per car, in such diverse areas power systems, transmissions, entertainment, in-vehicle networking and more. SOI will experience especially high growth in electrification, information/entertainment, networking, 5G, AI/edge computing and ADAS. He then went on to give some history and an extensive overview of the major trends and highlights we’ve seen over recent years. He finished by giving examples of convergence across the supply chain with IC manufacturers working with automakers to lower power, increase processor performance and advance 5G.

Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Tony King-Smith, Executive Advisor at AImotive and Mark Granger, GF’s VP of Automotive Product Line Management (Photo courtesy VeriSilicon)

GF’s Mark Granger addressed the rapid development of automotive electronics. In certain areas, he said, he sees growth rates of over 20%. They are working on building the Chengdu ecosystem, especially for design, and in cooperation with the rest of the supply chain. Furthermore, he reminded the audience, when you talk about cars, travel implies that you also talk about IoT as well as things like infotainment and integrated radar ICs. In addition to cost and power efficiencies, the AEC-Q100 standard for IC reliability in automotive applications is also pushing designers to turn to FD-SOI. In the GF meeting with Chengdu government officials (referenced above in deputy mayor Fan Yi’s talk), he too confirmed their support of FD-SOI as a key technology for China. GF is currently cooperating with about 75 automotive partners, he said, and the company is looking to increase cooperation with partners in the Chengdu region.

Tony King-Smith talked about the 22FDX test chip AImotive is doing with Verisilicon and GF. In case you missed it, in June 2017 AImotive announced its AI-optimized hardware IP was available to global chip manufacturers for license. AiWare is built from the ground up for running neural networks, and the company says it is up to 20 times more power efficient than other leading AI acceleration hardware solutions on the market. In the same announcement, they revealed that VeriSilicon would be the first to integrate aiWare into a chip design,and that aiWare-based test chips would be fabricated on GF’s 22FDX. The chip is expected to debut this year.

While the afternoon agenda was not specific to FD-SOI, it did focus on the “smart cockpit” and “intelligent driving”, with talks by nine leading players in China’s automotive IC and investment communities.

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Note: Many thanks to the folks at VeriSilicon, who wrote up this event for their WeChat feed, and shared photos with us here at ASN.

ByAdele Hars

Industry 1st and It’s on FD-SOI: ARM’s eMRAM Compiler IP for Samsung’s 28FDS

Per Arm, the industry’s first eMRAM compiler IP is now on Samsung’s 28nm FD-SOI technology. The announcement was made in a post by Kelvin Low, VP Marketing for ARM’s Physical Design Group (read it here). He said that ARM has successfully completed their first eMRAM IP test chip tapeout. The Arm eMRAM compiler IP will be available from 4Q 2018 for lead partners.

Samsung Foundry’s 28nm FD-SOI process technology is called 28FDS. eMRAM (which stands for embedded MagnetoResistive RAM) is a novel non-volatile memory (NVM) option positioned to replace incumbent NVM eFLASH, which has hit its limits in terms of speed, power, and scalability.

Arm’s new eMRAM compiler IP gives Samsung’s 28FDS customers the flexibility to scale their memory needs based on the complexity of various use-cases, explains Low. “What drives the cost-effectiveness of this compiler IP is that eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below,” he says. “Also, the eMRAM compiler can generate instances to replace Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM) and slow SRAM/data buffer memories with a single non-volatile fast memory – particularly suited for cost- and power- sensitive IoT applications.”

A key slide shown by Arm at the 2017 SOI Consortium’s Silicon Valley Symposium (Courtesy: Arm and the SOI Consortium)

At the SOI Consortium’s 2017 Silicon Valley Symposium, Arm said that they were stepping up their support of FD-SOI (read about that here) – and clearly they are! At that event, Arm VP Ron Moore gave a great presentation, which is freely available on our website: Low Power IP: Essential Ingredients for IoT Opportunities.

Samsung, btw, has been offering 28FDS for about three years now. (ASN did a 3-part interview with Kelvin Low back in 2015 when he was a senior director of marketing for Samsung Foundry. It’s still a useful read – you can get it here.) As of last fall, Samsung said it had taped out more than 40 products for various customers. And at the SOI Consortium’s 2018 Silicon Valley Symposium, Hong Hoa, SVP said they’d already taped out another 20 this year (read about that here).

Samsung says the write speed of their eMRAM is 1000x faster than eFlash. They actually announced the industry’s first eMRAM testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here). They also did an eMRAM test chip with NXP. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it above or on YouTube here.)

As noted in ASN’s Silicon Valley 2018 symposium coverage, the basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDS platform will be ready by the end of this year, and eMRAM beginning in 2019.

ByAdele Hars

Dolphin Showcases New EDA Tool for FD-SOI – More THINGS2DO Results

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.

THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)

“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”

The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.

Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.

The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.

Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.

Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”

See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF’s 22FDX.

ByAdele Hars

More than EDA – Cadence Talks About Designing With FD-SOI

EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.

Here’s a recap of what the Cadence folks said. (I’ll cover the Synopsys and Silvaco presentations in my next posts.)

Design Wins

At the Shanghai FD-SOI Forum. Dr. Qui Wang, VP & Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.

In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.

To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.

Cadence Has It All

Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World — Cadence EDA & IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.

He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.

His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow).

EDA requirements for FD-SOI are complete. (Courtesy: Cadence & SOI Consortium)

Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)

Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.

For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry’s PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.

And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).

Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.

ByAdele Hars

We’re Doing It! FD-SOI Ecosystem Shines in Tokyo (Day 1)

The FD-SOI ecosystem is strong. This was made clear at the recent Tokyo SOI Workshop, organized by the SOI Consortium. The event was spread out over two days, and most of the presentations are now posted (click here to access them).   To cover the full scope of the workshop will take (at least) a couple ASN posts. So let’s start with Day 1, which was billed as the “FD-SOI Ecosystem” day.

A full house for the 3rd Annual Tokyo SOI Workshop, Day 1, FD-SOI Ecosystem(Courtesy: SOI Consortium)

It kicked off with a full-house for an afternoon session in the Yokohama Landmark Tower hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem.

Silvaco:  FD-SOI EDA Pioneer

David Sutton, CEO of EDA provider Silvaco opened the session with his talk, TCAD, EDA & IP to Support FD-SOI. Silvaco has deep FD-SOI roots, having supported Lapis Semi (formerly Oki) in its first forays into the technology – and that was back in 2002! The company is on a growth run this year, having acquired four companies, including IPextreme.

FD-SOI, he said, has been shown to be cost-effective. The capacity is in place, and it’s getting design wins. Silvaco’s full suite of EDA and custom CAD tools for FD-SOI cover the complete design flow from TCAD to sign-off. Their IP is very strong, he said, especially in automotive (including CAN IP), and their partnerships with key players like IBM and NXP are long running. In fact, Silvaco commercializes IP from NXP and others.

GF: FD-SOI Primetime

We got some great insights from Gregg Bartlett, GlobalFoundries’ SVP of the CMOS Business Unit, in his presentation FDX (FDSOI) Goes Mainstream –  Roadmap for Product Competitiveness (it’s posted – click here to download it). “It is primetime for FD-SOI,” he said, and since one technology does not fit all, they’re redefining the mainstream.  GF’s first FD-SOI offering, 22FDX, was qualified in March, and 12FDX will be taping out in the second half of 2018. They’ve currently got over 80 active engagements.

(Courtesy: GlobalFoundries, SOI Consortium)

FD-SOI will be strong in China, he said. GF and the Chengdu municipality recently announced they are investing more than $100 million to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. This will lower the barriers to entry and increase IP availability even further, he said. They’re looking to put 500 design engineers in place. Customer tape-outs of 22FDX will begin at the new fab there in 2H2018, with volume production expected to start in 2019.

He went on to drill down on FDX applications, focusing on four main areas:

  • mobility: application processors that need high performance, RF integration and significant power reduction

  • IoT: this was the target when FDX was first conceived, and it continues to be a point of significant investment by the company

  • RF and mmWave: for BLE (Bluetooth Low Energy), WiFi, ZigBee and integrated PA’s (aka power amplifiers – where they’re seeing some impressive numbers, he said)

  • automotive: Grade 2 is done, and Grade 1 is underway (these are industry ratings related to reliability at the high-temperatures you get under the hood and in hotspots in the passenger compartment).

Citing a slide of customer testimonials, he concluded that the ecosystem is really starting to work, adding that they’ve got the right technology for the right applications, and it’s the right path for them to be on.

Invecas IP & Services

Invecas has been working on 22FDX since 2015 through a strategic partnership with GF. They’ve optimized IP and offer ASIC services, explained Bhaskar Kolla, the company’s Sr. Director of BizDev & Customer Engineering. His presentation, Invecas IP Portfolio in 22FDX is posted – click here to get it. It’s full of detail (standard cells, memories, analog & IO, and interface), so you’ll really want to check it out. The IPs are silicon proven and validated; the results are available, he said.

The foundation IPs are sponsored by GF, so they’re free to customers and cover a broad array of calibrations. They include forward and reverse body biasing (FBB and RBB) and body bias generator IP. Customers are really taking advantage of this, he said, citing as an example one that’s going for 2.5GHz by leveraging FBB.

Custom IP for analog & IO is a place they’re seeing a lot of interest, he continued, and on which they’re doing more and more work with clients. And their Interface IP is in a lot of silicon, especially for customers that are area sensitive. In fact, they’ve developed their own Interface IP demo platform in-house, from build through test and compliance checks.

In moving to FD-SOI, customers are seeing significant PPA improvements, he said. In one of the customer use cases for a high-level IoT product he cited, the customer requirements were easily achieved: cutting leakage in half, dynamic power consumption by roughly a third and area by 20%.

Leti: boosting at 10nm

There’s so much technical detail on performance boosters in Laurent Grenouillet’s presentation, FD-SOI: a Low Power, High Performance Technology Scalable Down to 10nm, you really just have to look at it yourself – click here to get it. A CMOS & Memory Integration Expert at Leti, he did a quick review of 28-22-14nm, then took a deep dive into the myriad of performance boosting options for 10nm, including impressive benchmarking regarding the effectiveness of mobility boosters on FD-SOI vs. FinFET.

Here are the boosters he detailed for 28-22-14nm:

(Courtesy: CEA-Leti, SOI Consortium)

Interestingly he noted that with each node, the thickness of the insulating BOX layer of the SOI wafer scales down, and as it does, back bias efficiency improves even more.

Here’s what he then covered for 10nm (and detailed with data packed in the 20 slides that followed):

(Courtesy: CEA-Leti, SOI Consortium)

FD-SOI is the sweet spot when you need lower power, lower cost, more sensing (analog), more comm (RF), more flexibility and more energy efficiency, he concluded – and he provided powerful data to back that up.

Attopsemi’s non-breaking fuse

I-fuseTM: the best OTP of Choice for FD-SOI and sub-14nm nodes was the topic of a talk by Attopsemi Technology’s Chairman, Shine Chung (you can get the ppt here). The company recently joined GF’s FDXcelerator partner program. OTP stands for one-time programmable memory, and I-fuse is different from other OTP technologies (notably NVM and e-fuses), he explained, in that it’s a non-breaking fuse with ultra-high reliability even in high-temp conditions. It’s been qualified by companies worldwide and is in volume production.

He’s a big fan of FD-SOI because it offers the best RF integration, small form factor, ULP and low cost. Want to make a cellphone as small as a watch? Then you need FD-SOI, he quipped with a tip of the hat to a Dick Tracy image. The fact that FD-SOI has a lower junction breakdown than bulk makes I-fuse the best choice for it, he said. You just program a gate as a fuse.

Get it out the door, fast!

During breaks (on both days!), everybody was talking about the terrific Product Design Methodology presentation by Christophe Tretz, the SOI Consortium’s design guru (and longtime IBM guy). In fact, Christophe has agreed to write it up for ASN in the weeks to come, so don’t miss that. You’ll want to look at the whole presentation — click here to get it.  In the meantime, here are some highlights.

(Courtesy: SOI Consortium)

He suggests designers consider an incremental approach in which FD-SOI benefits accrue. “No, you don’t have to know everything about the technology to use it,” he began (especially addressing those in smaller design teams and houses). “The ecosystem is there. Everything you need to use it is there.”

He used a number of cases to explain.

  • Case 1: a simple, digital SOC – you get significant power savings just by reusing existing library blocks and doing minor recompile.

  • Case 2: RF/mixed-signal – turnaround time is very fast (Analog Bits, for example cut leakage by 5x in a port that took just three months). FD-SOI gives analog designers a great new thing to play with for big power savings – and they learn fast.

  • Case 3 (= Cases 1 + 2): “complex” SOC with RF blocks – rework the RF blocks, but reuse library elements for the digital part without a lot of design effort. You get significant power savings very easily.

  • Case 4: a more complex SOC – in this case, you optimize or customize a few blocks in the first design pass, but then optimize/customize more blocks in subsequent design passes. It just keeps getting better and better.

  • Case X: a fully optimized SOC. This takes more time, but you can do parts in parallel and get dramatic results – especially if you use body biasing.

He then looked at the state of the ecosystem:

  • three fabs are ready

  • we have the tools (Synopsys, Cadence, Silvaco)

  • the libraries are there and ready to use

“You don’t have to learn everything to get your product out the door,” he concluded. “You don’t have to do it all at once: you can do it incrementally. Within a few months, you’ll have a nice product, and as you do new products every six months, each time you can re-use, but also tune for more improvements.”

In short: just do it!

So that’s a recap of Day 1. Next post (or posts?) I’ll recap Day 2. Stay tuned!

ByAdele Hars

New Advanced NV Memory IP for FDSOI – Attopsemi Joins GF’s FDXcelerator Program

There’s a new memory IP specialist on board for the FDSOI ecosystem. Attopsemi Technology has joined GlobalFoundries’ FDXcelerator™ Partner Program (read the press release here). Attopsemi is ensuring that its scalable, non-volatile one-time programmable (OTP) memory IP is compatible with GF’s 22FDX® technology. Their leading-edge I-fuse™ OTP IP is a fuse-based OTP technology that can guarantee zero-program defect, and offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current compared to traditional e-fuse technologies. This advanced OTP targets customers and designers working on harsh, demanding applications such as automotive, 3D IC, and IoT.

“Attopsemi’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

ByAdministrator

Silicon Valley FD-SOI Symposium Promises Best Ecosystem Line-Up Ever: ARM, Foundries, EDA, Designers, Experts & Users (13 April – free and open to all who sign up)

The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.

To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.

FDSOI_SanJose13Apr16It’s really a terrific agenda – check it out:

08:00AM – 09:00AM – Registration

08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium

09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything

09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO

10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption

10:30AM – 10:50AM – Coffee Break

10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit

11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP

11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing

12:20PM – 1:40PM Lunch

1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division

2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO

2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP

3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division

 

3:30PM – 4:00PM – Coffee Break

4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager

4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering

4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”

5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D

5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse

6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium

Seriously – this good. Plus during breaks you’ll want to check out the poster sessions with GSS, sureCore, Soitec, SEH and the SOI Consortium.

Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:

Doubletree Hotel San Jose

2050 Gateway Place

San Jose, California 95110, USA

If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org. logo_soiconsortium