Cadence has announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. (See Cadence press release here.) On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, which the company says is an ideal solution for inter-chip USB applications. Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process
Synopsys has announced that STMicroelectronics has standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization. As noted in the press release (read here) ST has a unique processor architecture made possible through their FD-SOI process technology. An FD-SOI device can operate at significantly higher frequencies than an equivalent, traditional, bulk CMOS device. It can also run very fast at low voltages, providing much higher energy efficiency. The close collaboration between the ST design teams and Synopsys has led to a compelling implementation solution that fully exploits the performance and power promise of FD-SOI technology and provides the throughput needed to meet tight time to market windows.
Interested in energy-efficient SOCs? At the IP-SOC Conference last fall, STMicroelectronics’ Giorgio Cesana presented examples of the technological competitiveness of FD-SOI IP for memories, cores, ultra-low voltage and analog.
Here’s a brief recap. The complete presentation, entitled “FD-SOI Technology for Energy-Efficient SoCs: IP Development Examples” is available on the Design & Reuse website (click here to view it).
Memory is the proverbial canary in the coal mine for chip designers. To run reliably, pairs of transistors can’t be mismatched – and this becomes more critical with the lowering of the supply voltage (Vdd), nowhere more so than in memory. FD-SOI decreases mismatching by 40% compared to low-power (LP) bulk, and decreases leakage by a factor of 8. Soft error rates (SER) are 100x better in FD-SOI than in bulk. And of course, being able to run at lower voltages can make a significant contribution to battery savings in portable devices.
In the example of a dual ARM A9 subsystem architecture, ST’s IP is used to generate programmable body voltages, enabling a CPU to run at 300 MHz with a 0.5V supply voltage. Increasing the supply voltages increases the performance: up to 2.3 GHz at 1V, and on to 3 GHz at 1.34V. And with forward body biasing (FBB), which is only possible in FD-SOI, you get 1GHz at 0.6V when you need it.
Dynamic process scaling, thanks to extended body biasing, allows dynamic switching between high-speed and static-power optimizations. In a multi-core context the effects are dramatic.
Ultra-Low Voltage Apps
For things like medical devices and Internet of Things (IoT) apps, the ultra-low voltage design enabled by FD-SOI should be a key differentiator.
The presentation shows that ST is particularly pleased to emphasize what analog designers can do with FD-SOI. For example, in a switch the resistance ratio between on and off (Ron/Roff) is 10x better in FD-SOI than in bulk or FinFETs. Power signal gains are improved by 6x without using pocket implants, and matching is better in short-channel devices because there is no channel doping.
Here at ASN, we’ll have lots more good news and useful information coming your way from the FD-SOI design community in the weeks and months to come. So if you haven’t signed up for a free subscription* yet, now’s the time! Just click here and fill in the form.
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Concluding, “Faster, Simpler, Cooler,…and Cheaper: FD-SOI technology should get very good traction in the near future!”, semiwiki blogger Eric Esteve has kicked off a very lively conversation. Within a few days of posting Faster, Cooler, Simpler, could FD-SOI be Cheaper too?, there were almost 20 comments, with lots of good supplemental information from well-informed participants. This must-read piece marks the latest in a series of high-profile semiwiki posts on FD-SOI.
Good news for the SOI ecosystem: SOI wafer suppliers Soitec and SunEdison (formerly MEMC) have ended their longstanding legal feud and entered into a patent cross-license agreement (press release here). The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all their outstanding legal disputes.
For Soitec, it represents a milestone for the SOI ecosystem, said Christophe Maleville, SVP of the company’s Digital Electronics Division.
For SunEdison, it adds to the company’s current SOI product capability, said Horacio Mendez, VP of the company’s Semiconductor Advanced Solutions division.
The agreement covers wafers for device architectures such as partially-depleted SOI (PD-SOI), fully-depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.
The two companies have also agreed to grant each other the right to use their respective wholly-owned patents for research and development purposes. This applies to the development of products with advanced semiconductor materials beyond silicon that enable the fabrication of high-mobility channels for advanced generation digital applications.
The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.
The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).
Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.
The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)
The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.
sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).
An impressive hot topics session was dedicated to RF CMOS.
J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.
Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.
The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).
The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.
The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.
3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.
The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.
Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.