Dr. Wolfgang Mueller has joined Innovative Silicon, Inc. (ISi) as director of device engineering and process integration. ISi is the developer of the SOI-based Z-RAM® zero-capacitor floating body memory (FB) technology.
Dr. Mueller is a 30-year industry veteran, who spearheaded a number of memory innovations including the development and implementation of “buried wordline” DRAM technology at Qimonda AG.
Craig Factor named VP legal affairs and general counsel.
Z-RAM® developer Innovative Silicon, Inc. (ISi) has named Dr. Victor Koldyaev as the company’s first Innovative Silicon Fellow.
Dr. Koldyaev joined ISi in August 2007 as director of device, material science and front end-of-the-line (FEOL) integration, where he is responsible for over-seeing process architecture development for Z-RAM memory technology across various applications.
ISi CEO Mark-Eric Jones particularly cited Dr. Koldyaev’s innovative thinking in bringing up Z-RAM for sub-45nm nodes.
In other company news, ISi announced that Craig Factor has joined the company as vice president of legal affairs and general counsel. Among his previous positions, he was general counsel at Artisan Components, a public semiconductor intellectual property licensing company that was acquired by ARM Holdings.
Z-RAM is ultra-dense, SOI-based memory technology for stand-alone DRAM and embedded memory applications.
Two more prestigious awards for Innovative Silicon Inc. (ISi) and its SOI-based Z-RAM® memory IP: a Technology Pioneer 2008 from the World Economic Forum and Audemars Piguet’s “Changing Times ‘Next Gem’ Award”.
Innovative Silicon (ISi), the developer of Z-RAM® ultra-dense memory intellectual property (IP), is on an awards roll.
The company recently announced that IEEE Spectrum Magazine readers named Z-RAM the number one winning technology in its “Winners and Losers” edition. Over 50 percent of nearly 1,000 voting readers indicated that ISi should be selected for the award. As such, ISi received the EE Times and IEEE Spectrum Emerging Technology ACE Award. Read More
The co-inventor of Z-RAM explains the technology.
As a Z-RAM – zero capacitor RAM – memory technology bit cell uses only a transistor plus the floating body effect inherent in SOI processing (see Figure 1), it typically measures only 15-20F² (where F is the technology minimum feature size). Read More
• Innovative Silicon Inc. (ISi), the developer of Z-RAM® high density memory IP, announced that it has recruited semiconductor memory and SOI luminaries Dr. Jean-Pierre Colinge, Dr. Michel J. Declercq, Dr. Richard C. Foss, Dr. Carlos Mazure, and Mark McDermott to participate in the company’s newly formed Technology Advisory Board.
The widening availability of tools and services is good news for designers in the fabless/foundry arena considering the move to SOI.
Leading foundries have made the investments in manufacturing on SOI. Those that have taken the final steps – finalizing electrical characterization, constructing SPICE models, integrating design tools and building libraries – are winning business.
Chartered, for example, is producing SOI-based chips for AMD, the Microsoft Xbox®360, Via, and others in partnership with IBM. TSMC, meanwhile has announced an SOI version of its Nexsys 65nm process technology for next year.
For the high-performance fabless community, IBM itself was the first to open SOI doors to its foundry customers. Ghavam Shahidi, Director of Silicon Technology, IBM Research Division, says they see the full range – from customers that do the whole thing themselves, just getting the IBM-specific SOI IP, to those who essentially hand off the whole project to the IBM services group. Asked how big a challenge the move to SOI is, he says, “It’s not a big deal – it seems scarier than it is.”
As far as those low-power customers worried about the added cost of SOI wafers, he suggests that if they were to consider the broader picture and include things like cooling, they might find it a more cost-effective solution.
Design flow involves a series of iterative steps subject to rules and constraints – many of which are different when devices are built in SOI. SOI-specific IP is needed at each step, especially:
• In support of the logic synthesis tools used to transform the high-level RTL design into a gate-level netlist (which is the collection of “standard cells” and their electrical interconnections specific to the foundry that will do the manufacturing).
• And in the placement and routing tools to layout the chip. Either the design team has to develop SOIspecific expertise (a substantial investment), or license intellectual property (IP) from a third party (the foundry or an IP vendor).
By licensing the requisite IP, designing-in SOI becomes a transparent process. As the designer generates netlists and optimizes placement and routing, the SOI IP is applied via standard EDA tools from companies like Cadence, Synopsys and Magna.
TCAD from Synopsys, for example, can model the SOI technology from the process and device simulation standpoint, so performance of SOI and bulk silicon can be compared before choosing the right technology for the design, says a company representative. Also, engineers can optimize the SOI technology by using TCAD simulation before running costly experimental wafers.
Says Francois Thomas, Europe ICD & DFM Field Marketing Director for Cadence Design Systems, “SOI uses nearly standard processes and design but with better performance. The real difference appears for cell creation, analog simulation and DRC and parasitic extraction.”
Recently three new SOI IP and design services suppliers have helped bring SOI design to a wider community.
Soisic. Working with companies that pioneered SOI, Soisic developed extensive design expertise and intellectual property (IP), which is now available to any ASIC designer. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed
Innovative Silicon (ISi). ISi has harnessed the SOI “floating body effect” for memory cells that are twice as dense as existing DRAM and five times as dense as existing SRAM. This proprietary “Z-RAM™” (for Zero capacitor DRAM) technology uses standard SOI logic processes without new materials or extra process or masking steps. For most SoC and microprocessor ICs, this results in SOI being a lower-cost solution than bulk silicon. AMD is the first licensee.
CISSOID. As a fabless player, CISSOID designs custom analog, mixed and digital ASICs, with a specialty in SOI-based high temperature components for oil & gas, aeronautics, space and automotive applications. For low-power and RF applications, CISSOID offers design services, IP development and consulting for optimization of SOI analog and RF circuits.
For designers of mixed-signal, analog and RF devices, a growing number of major foundries have been actively promoting their SOI services.
For example, Honeywell offers RF SOI foundry services, supported by a comprehensive tool set and optional design services. The company points out that the SOI-enabled integration of mixed signal and high-voltage applications with complex control functions performed at low power on a single chip ultimately reduces cost.
Others like Atmel promote their SOIbased smart power foundry services for automotive, telecommunications and consumer electronics, noting that using SOI cuts the die-area in half compared to standard bulk technology. The X-Fab foundry service offers SOI-based analog/mixed-signal and MEMS.
All things considered, SOI is now well within the grasp of the greater chip design community.
ISi’s memory technology helps designers achieve speed increases and power savings at no extra cost.
It is well-accepted that SOI processing offers significant benefits in terms of speed and low power. Moreover, as the industry moves to the 65 and 45nm nodes, many analysts predict that bulk CMOS – so long the technology of choice – will be unable to scale due to inherent issues such as leakage, forcing system-on-a-chip (SoC) and microprocessor manufacturers to shift to SOI. Taking these factors into account, Gartner-Dataquest predicts a CAGR of 41.2 percent for SOI wafers between 2002 and 2008, and many leading companies such as AMD are already delivering chips built on SOI technology.
One of the last remaining impediments preventing companies from adopting SOI is cost. However, with the introduction of Z-RAM (Zero Capacitor DRAM) memory technology by Innovative Silicon Inc. (ISi), this last barrier is removed. Z-RAM memories are so dense – up to twice the density of existing embedded DRAM and five times denser than current embedded SRAM – that the typical processed wafer cost penalties of 8 to 15 percent that are usually associated with SOI are more than offset by the financial savings that can be realized by smaller die sizes.
SOI is already a great choice, and when used in combination with ISi’s Z-RAM memory IP, not only can designers achieve speed and power improvements, but they can save money, too. Depending on how much memory is put on-chip, the die cost of SOI + Z-RAM will be 10%-40% cheaper than the same chip designed in bulk CMOS.
By removing the cost obstacle, Z-RAM is enabling SOI to move deeper into the mainstream.
Z-RAM + SOI can save > 40%.
There is no doubt today that the industry, led by the microprocessor segment, is moving to take advantage of the lower power consumption and higher performance of SOI compared to bulk wafers. Read More