Tag Archive markets

New Semico Study on SOI Apps, Opps & Markets

Research and consulting group Semico has issued a new report entitled SOI Update 2015: Finding New Applications (for information on getting a copy of the report, click here). As described on the Semico website: “With the recent growth in RF-SOI for switches and integrated solutions for RF functions such as power amplifiers and transceivers, the opportunities for growth in SOI wafer demand have once again garnered a lot of attention. In addition, as the industry transitions to very complex and expensive finFET technology, SOI is providing a high performance, low power option to semiconductor vendors who do not want take on the challenges of finFETs. This report explores the markets, products and outlook for SOI wafer adoption over the next five years.”

Huge Success of Semicon China: Opportunities in a Fast-Changing Landscape

SemiconBannerlores

Semicon China (Shanghai, 17-21 March 2015) was an awe-inspiring event.   The sheer size and the energy were dazzling. But it was the investment plans prompted by the government’s injection of RMB 120 billion (US$19.6 billion) last fall in seed money for the industry with supporting local funds pouring in that was clearly the source of a lot of adrenalin and M&A talk.

 

China’s industry is in high gear, still posting double-digit growth. But here’s the rub: while China consumes about half of the world’s roughly US$ $350 billion in chips (2015, WSTS), fabs in China only account for 2.5% of worldwide revenue. They’d like to see that change in a big way, and fast.

 

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

XMC slide shown during Semicon China 2015 show the challenges facing fabs in China.

Hence Beijing’s IC Investment Fund, which is expected to continue to be expanded. SEMI estimates that the total government (central plus local) funds will reach US$100 billion, plus it’s prompting the creation and growth of additional local government and industry funds. (Dr. Adam He at SEMI has done an excellent job explaining Beijing’s investment strategy – you can see his summary here.) New VC funds are popping up everywhere, and existing ones are being augmented.

 

Which is why everybody was calling it the best time the industry’s ever seen. In his talk, Handel Jones of IBS, called it a once-in-a-lifetime opportunity.

 

This should represent significant opportunities for the SOI ecosystem in China. China foundries are offering RF-SOI already (click here to read about the Shanghai RF-SOI Workshop). And it is worth noting that China’s R&D institutes have deep expertise in all things SOI.

 

FD-SOI is an important topic (click here to see an ASN piece on FD-SOI by a professor at a top Beijing institute from last year, and here for more about the recent Shanghai FD-SOI workshop). China’s designers are hot on FD-SOI, too. (Did you hear about how the Beijing cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015? Read about it here.)

 

SOI-based MEMS, power, and sensors products are also already produced in China’s foundries. In fact SOI was a strategic focus by key institutes like SIMIT under the national “Innovation 2020” 5-year plan launched in 2010.

 

In terms of SOI wafers, China’s wafer leader, Simgui also works closely with Soitec, the world’s SOI wafer leader. Not surprisingly, theirs was a busy stand at Semicon China.

 

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

Simgui, China’s SOI wafer leader, had a busy stand at Semicon China 2015.

 

The Hot Topic: M&A

 

During the keynotes and industry sessions, M&A were central themes, as China looks beyond its borders for expertise. Hardly a talk went by that didn’t touch on this topic, all emphasizing that 1 + 1 > 2, and hammering home the importance of holding on to top talent in takeover scenarios. With each new slide, a sea of smartphones raised above the crowd to capture the onscreen tips.

 

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

It was standing-room-only at the Semicon China 2015 Tech Investment Forum.

 

In fact, with the IC Investment Fund taking center stage, the head of China Merger & Acquisition at Goldman Sachs gave the audience a primer on the M&A process. China, he noted, is now number two for M&A worldwide, just behind the US. While in the past the activity was “inbound”, China’s companies are now active on a transnational scale. This year will be an M&A record breaker for the semiconductor industry in China.

 

China’s expats are returning in droves from abroad, founding new companies. New industrial parks like the one out by the Shanghai airport are attracting major investors.

 

 

 

Big Show, Small World

 

This was the biggest Semicon ever, with 2750 booths covering 57,000m2 (over 600,000 sq. ft – more than three times the size of West) and over 50,000 visitors (almost twice what they got at West+Intersolar last year).

 

But Semicon China also had its small-world moments that show just how far SOI is reaching. Consider this. I was on the metro in Shanghai, heading over to Semicon, reading the show program. The guy next to me asked a question about the show (he was heading there, too), and we got to chatting.

 

It turns out he’s the founder of Trinamic, a German company that designs chips for motion control. They have just started an SOI project with X-fab as the foundry. He’s very clear and enthusiastic about what he expects SOI to do for them. It’s for a high-volume app in small, precision motor control for things like video surveillance cameras.

 

This is an encouraging indication of just how far the SOI ecosystem is reaching! (We have an interview coming up with the folks at X-fab, btw, so keep an eye out for that.)

 

We’ll also have lots more from China, including interviews and profiles of the institutes and companies that are major players in the SOI ecosystem there. It’s truly an incredible place to be right now.

 

Strong uptick in FD-SOI patent activity, according to KnowMade report

There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure).  The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies).  More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families.  Following a rush of activity about 10 years ago there was a dip, but activity over the last couple of years has once again been very strong.

The report provides a comprehensive overview, essential patent data for fully depleted SOI, plus a searchable database with links.  It identifies more than 30 patent holders of FD-SOI related intellectual property, providing in-depth analysis of key technology segments and key players. “The major proponents of the FD-SOI technology have strong IP arms, but other unexpected players known as not supporting FDSOI [including TSMC and Intel] are also present,” notes the report.

TowerJazz — Interview With SVP Marco Racanelli: What’s Driving Strong SOI-Based Design Wins?

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

Dr. Marco Racanelli, TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group

 

 

TowerJazzLogo_2014LR

 

 

 

 

ASN recently spoke with TowerJazz SVP Marco Racanelli about when the specialty foundry leverages SOI – and why.

Advanced Substrate News (ASN): Can you tell us briefly about TowerJazz’s overall vision and position in the market? 

Marco Racanelli (MR):  TowerJazz is the foundry leader for the manufacture of specialty semiconductor devices.  By “specialty” semiconductor devices, we mean those that require technology with some degree of specialization beyond commodity CMOS, for example in applications such as analog, RF, power, CMOS Image Sensor, and MEMS.  We invest in specialty process technology and manufacturing capacity around the world to fuel our growth (today we have manufacturing facilities in the US, Israel and Japan).

The TowerJazz fab in Newport Beach, CA.

The TowerJazz fab in Newport Beach, CA.

ASN: What kinds of chips does TowerJazz propose customers put on SOI? Why? 

MR: SOI on high resistivity substrates provides excellent RF isolation for customers working on front-end modules (FEMs) for wireless communication products.  Specifically for RF switches, thin device silicon layers result in low junction capacitance which is favorable for achieving high isolation.  We have had some customers leverage our SiGe BiCMOS technologies on SOI to integrate improved RF switching capabilities and achieve better isolation among circuit blocks.  Finally, some TowerJazz customers use thick film SOI for MEMS.  The silicon layer in SOI is used to fabricate beams for electro-mechanical structures and devices, e.g. MEMS resonators.

ASN: What are the growth drivers (end-markets, trends) for your SOI-based services? 

MR: Each generation of smart phones has required increasing numbers of RF ports to support multiple standards and functions e.g. 3G, 4G, 802.11, diversity antenna.  The need for longer handset battery life is driving implementation of RF-SOI based antenna tuner products to improve antenna efficiency.

 

Click to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

Click image to enlarge. (Courtesy: Techinsights’ Teardown.com and IEEE S3S Conference)

ASN: What are the advantages in moving to SOI-based technologies? 

MR: In some markets such as FEMs, the performance advantages of SOI are required to enable these RF products in CMOS; bulk technologies simply can’t provide the required isolation and low capacitance to meet the most demanding 4G/LTE specifications.  Thicker film SOI can support SiGe bipolar devices with significantly lower collector-to-substrate capacitance than their bulk counterparts.  In high voltage products, SOI dielectric isolation can simplify the design process, reduce latch-up risk, and allow a much more compact design than junction-isolated technologies.

Inside the TowerJazz Newport Beach Facility (Fab 3)

Inside the TowerJazz Newport Beach Facility (Fab 3)

ASN: Are there particular regions where you see especially high growth for SOI-based offerings? 

MR: We see broad adoption of SOI in all major phone platforms.  Our strongest growth and largest market for SOI is in the US although we see some Asia customers as well. The end customers are more evenly distributed between the US and Asia primarily.

ASN: Last year, you announced your RF-SOI had the industry’s best figure of merit for antenna switch and antenna tuning applications. What are you seeing there in terms of design wins? 

MR: We are seeing very strong design wins and production ramp of SOI in our factories.

 

American Semiconductor's  FleX-MCU™ product family leverages an SOI starting wafer.  (Courtesy: American Semiconductor)

American Semiconductor’s FleX-MCU™ product family leverages an SOI starting wafer.
(Courtesy: American Semiconductor)

ASN: American Semi partnered with TowerJazz on flexible ICs, which leverage SOI.  What sort of applications is that technology going into?  

MR: The potential for flexible ICs is very broad. For Aerospace and Defense, key areas of interest are ‘wearable’ circuits, introducing ICs and systems into soldiers’ field clothes and gear, creating a radar system that conforms to the entire body of an aircraft, sea vehicle, or any UAV or drone.  The ideas can be countless – the path is to reduce or eliminate the rigid form and fit of mobile electronics and integrate these electronics into a lighter weight, smaller and more flexible material.

ASN: Cavendish Kinetics announced that they’d be collaborating with you on RF-MEMS for mobile, which could be on SOI.  Is that available, and if so, can you tell us about it?

MR: We continue to work with Cavendish and have announced impressive reliability results with their devices; these are available through Cavendish directly.

ASN: Can you tell us more about the forthcoming 0.18 TS18SOI integrated power platform? 

MR: This platform is targeting a number of applications, the dominant one being in automotive and will include high-voltage devices, 0.18um CMOS for integration of digital and power management functions along with non-volatile-memory.  SOI in this case helps isolate the devices from the substrate allowing flexibility in applying voltages without turning on junctions that can lead to leakage or latch-up and in some cases helps reduce die-size by improving isolation allowing devices to be closer together.

ASN: Looking down the road, where/how do SOI-based technologies fit into your outlook for the future?  

MR: SOI particularly for RF is a significant focus for TowerJazz and we continue to invest in new technology and propagating the technology we have to multiple factories to increase capacity available to our customers.  While RF dominates our SOI consumption, we also see a good future for SOI in power management and MEMS and other sensor applications.

 

TGS2014_logo-LR

 

 

 

 

TowerJazz will be presenting its SOI and other processes at its upcoming Technical Global Symposiums (TGS) taking place in Europe (18 September 2014), the US (19 November 14) and Japan (10 December 2014). To find out more and register for TGS, please visit: http://www.towerjazz.com/tgs/

 

 

 

~ ~ ~

Dr. Marco Racanelli has served as TowerJazz Senior Vice President & General Manager, RF & High Performance Analog Business Group and Aerospace & Defense Group since September 2008. Previously, he served as Vice President of Technology & Engineering, Aerospace & Defense General Manager for Jazz Semiconductor.

 Prior to Jazz, Dr. Racanelli held several positions at Conexant Systems and Rockwell Semiconductor since 1996 in the area of technology development where he helped establish industry leadership in SiGe and BiCMOS and MEMS technology, and built a strong design support organization. Prior to Rockwell, Dr. Racanelli worked at Motorola, Inc., where he contributed to bipolar, SiGe and SOI development for its Semiconductor Products Sector.

 Dr. Racanelli received a Ph.D. and a M.S. in Electrical and Computer Engineering from Carnegie Mellon University, and a B.Sc. in Electrical Engineering from Lehigh University. He holds over 35 U.S. patents.

~ ~ ~

FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.

 

FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.

 

FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

 

The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.

 

Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.

 

FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

EU report: SOI-based technologies should play important role in capturing new markets

“High performing low power digital technology based on SOI” is an important part of the detailed plan submitted February 14th by the Electronics Leaders’ Group (ELG) to European Commission Vice-President Neelie Kroes.  (Press release here.) The group recommends the EU focus on:

  • Areas were Europe is strong – automotive, energy, industrial automation and security. The target is to double current production in the next 10 years.
  • New high growth areas, in particular Internet of Things (IoT) and the development of ‘Smart-X’ markets (e.g. smart homes, smart grids etc.).

The electronics industry CEOs said that Europe can capture up to 60% of new electronics markets, and double the economic value of semiconductor component production in Europe within the next 10 years.  “Advanced materials provide a path for breakthroughs and strong differentiation in silicon applications (Si-based, SOI, strain Si),” the report stated.

(It is worth noting that SOI is already well-represented in the areas cited for existing European strengths, with companies like NXP and ST producing enormous numbers of SOI-based chips for these markets.)

FD-SOI Is Cheaper, Too, Concludes semiwiki Blogger

Concluding, “Faster, Simpler, Cooler,…and Cheaper: FD-SOI technology should get very good traction in the near future!”, semiwiki blogger Eric Esteve has kicked off a very lively conversation.  Within a few days of posting Faster, Cooler, Simpler, could FD-SOI be Cheaper too?, there were almost 20 comments, with lots of good supplemental information from well-informed participants. This must-read piece marks the latest in a series of high-profile semiwiki posts on FD-SOI.

TowerJazz saw “a large amount of SOI design activity” in 2012

TowerjazzThe CEO of TowerJazz recently told analysts that in 2012, the company saw “a large amount of SOI design activity”, which he says will fuel revenue growth in 2013. Smart phone antenna switches that handle 8 to 14 different bands are moving from gallium arsenide to SOI, he explained.

IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm

In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).

For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology.  The industry thus faces a critical juncture in the shrink from 28nm to the nodes around 20nm (the precise dimensions of which vary by foundry).  Making the wrong technology decisions at ~20nm can cost wafer manufacturers and fabless companies billions of dollars.  It is therefore appropriate to analyze the cost factors for the different versions of 28nm as a baseline.

Multiple factors need to be considered with the migration to ~20nm, and the highly visible experience to date in attaining high yielding, volume production on 40nm and 28nm from the industry’s largest players provides visibility into what is likely to happen at 20nm bulk.

IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy.

For the purposes of our analysis, we consider die sizes of both 100mm2 and 200mm2. The flavors we considered are for high-performance (HP) and low-power (LP) chips. The technology options at the 28nm node are high-k/metal-gate (HKMG) bulk CMOS vs. FD-SOI. For the ~20nm node, we add FinFET to the analysis.

Savings realized by using FD-SOI at the ~20nm node

As shown in this graph, the savings realized by using FD-SOI at the ~20nm node is significant. Even once FinFETs have matured in Q1/2016, FD-SOI will still offer comparative savings of 50-60%, depending on die size.

Result: FD-SOI die cost less

At the 28nm node, if you only look at the processed wafer cost, the FD-SOI solutions are roughly 7% higher. However, yield issues and the net die/wafer at 28nm have a major impact on the bottom line. When defect densities and parametric yields are factored in, the FD-SOI solution results in a lower per-die cost: from 8% lower for the smaller, low-power chips, to 18% for large, high-performance chips.

At 20nm, however, the FD-SOI processed wafer cost is less than both bulk CMOS and FinFET processed wafers. The FD-SOI processed wafer cost advantage is then massively increased when yields are factored in.

Once ~20nm bulk FinFETs have matured in Q1/2016, FD-SOI will still offer comparative per-die savings of 50-60%.

Related FD-SOI advantages

Power/performance characteristics of FD-SOI will be 30% to 40% superior to bulk HKMG CMOS at 20nm. Analog porting of FD-SOI will be easier than with the other options because of the superior sub-threshold characteristics.

Today, FD-SOI is the only technology that can operate safely in the 0.6V to 0.7V range at 28nm.  While there is some reduction in performance, operating power is reduced, giving a very compelling performance-power advantage against other technologies.

Although the real competition is likely to be between FinFETs and FD-SOI at 20nm, FinFETs are a new technology (from a high-volume production perspective), with significant cost penalties even in Q1/2016.

Bulk HKMG CMOS will have low parametric yields at 20nm.  A major source of yield loss for bulk CMOS is that of random dopant fluctuations from transistor implants. These implants are not required for FD-SOI.  ~20nm FinFET structures will be high-cost to manufacture, and parametric yields will be low.

The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs.

So compared to bulk CMOS or FinFET, the FD-SOI option cuts ramp time by as much as half.

The faster ramp-up of wafer volumes combined with more predictable yield ramp-up provides additional cost benefits in using FD-SOI over other options at 20nm.

There is ongoing work to assess the further scalability of FD-SOI beyond 20nm to ~14nm and the initial results from IBM and Leti look promising.

Notes on starting parameters

For the purposes of this analysis, the processed wafer costs are derived from experience with leading foundries, for their costs in Q1/13 with eight metal layers (8LM).  (Selling prices of processed wafers will of course be higher and will include the gross profit margins of the foundry vendors.)  The processed wafer costs include $500 for the ultra-thin SOI wafer used in the FD-SOI process, and $129 for the bulk wafer used in bulk CMOS and bulk FinFET technologies. (While there is the expectation that the SOI wafer prices will be reduced in the future, this is not built into our analyses.)

We assume a high-volume production with utilization rates of about 95%. The bulk version assumes three threshhold voltages (Vt) in the core of the chip, and takes into account support for SRAMS and interfaces. The FD SOI cost is based on 1Vt level for the core and use of body biasing. Body biasing can give two additional Vt levels in the core, which is equivalent to bulk CMOS design options.

Wafer and die costs vary at different stages of maturity. For FinFETs, for example, the cost takes into account the relatively long time for metrology checking in the process and also the manufacturing complexity related to the FinFET structures.

SOI Demand Outlook

VLSI projects that a critical mass of expertise will support a fast transition to SOI designs at 32nm.

The semiconductor market recovery has helped to grow SOI demand in-line with the industry. Established applications such as AMD’s microprocessors, IBM’s high performance ASICs, and other manufacturers’ high performance computer, consumer  and communications products are moving through the 45nm process node to 32nm and beyond providing additional growth for SOI.

The design pressures of power dissipation, transistor leakage and high frequency performance are making it increasingly difficult to reap the rewards of smaller linewidth processes without recourse to SOI technology.

Applications moving into SOI include high-end computing, printers, set-top boxes, applications processors, games processors, baseband communications and high performance DACs. SOI is also finding its way into some analog devices.

The constraint on growth of the SOI market is no longer the availability of SOI wafers, and the cost adder for SOI is no longer the major hurdle that it was until recently.

However, the lack of design and production infrastructure is the main limiting factor.  Key industry players such as Soitec and IBM have been addressing this problem by establishing the SOI Industry Consortium. Additionally, ARM is now an enabling supplier in the SOI ecosystem, developing infrastructure and offering IP for designers to work with.

Annual sales of SOI (Source: VLSI Research, 2010)

The weight of these new resources is currently focused on 45nm designs but it is expected that this will establish a critical mass of expertise to support a fast transition to SOI designs at 32nm.

With each new process node SOI will become increasingly appealing for manufacturers of high-end devices that require low power consumption alongside optimum performance. Current major users IBM, AMD, Freescale, NXP, Sony and TI provide a solid foundation for others to follow into this market.