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Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

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Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

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Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

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Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

X-Fab Interview: SOI Solutions for analog/mixed-signal, high-voltage, high-temperature and MEMS Applications

X-FAB_logo_print_loresWith five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.

Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?

Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.

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Tilman Metzger, Product Marketing Manager for the X-Fab Group. (Courtesy: X-FAB)

Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.

ASN: When did X-Fab first start offering SOI and why?

TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.

ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?

TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.

Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.

ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?

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X-FAB headquarters in Erfurt, Germany (Courtesy: X-FAB)

TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.

Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.

ASN: When and why do your customers choose an SOI-based process?

TM: Typically, we see two types of SOI customers:

  1. Those that tried and failed a particular design in a BCD/Bulk technology and hence turned to a SOI solution; and
  2. Those that focus on SOI technology right from the start due to IC or system requirements (or past experience). Some of the challenges of such designs may include:
  • Very high temperature of 175-225°C
  • Resistance to EMI* or stringent EMC and ESD requirements
  • Latch-up concerns
  • Negative voltage swings / inductive loads
  • Stringent noise immunity / cross-talk requirements
  • Low leakage at high temperature
  • Aggressive time-to-market requirements

ASN: Can you expand on the time-to-market (TTM) issue a bit?

TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.

ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?

TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.

ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?

TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..

ASN: Can you tell us more about X-Fab’s SOI offerings?

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X-FAB cleanroom in Kuching, Malaysia, where the company runs their new XT018 SOI process. (Courtesy: X-FAB)

TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)

Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.

XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.

XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.

ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?

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X-FAB MEMS Foundry received the “MEMS Foundry of the Year” award at the Best in MEMS & Sensors Innovation Awards ceremony, as part of the MEMS Industry Group’s 10th annual MEMS Executive Congress® held in Scottsdale, Arizona in November 2014. (Courtesy: X-FAB)

TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.  

For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.

We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.

ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?

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Chips manufactured by X-FAB go into key automotive systems. (Courtesy: X-FAB)

TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.

We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.

We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.

ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?

TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.

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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.

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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge

**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.

SOI Radiation Detector Workshop – Registration Extended (SOIPIX2015 – June, Japan)

SOIPIX15International research teams working on or interested in the far-reaching SOIPIX radiation-detector project have a workshop coming up in June. The project was originally started by KEK* scientists to develop a new detector technology and quantum beam imaging for high-energy particle physics. As research teams around the world (including Japan, USA, China and Europe) joined to take advantage of the multi-wafer project runs, it soon expanded to include more applications. (To learn more about the program, click here.)

Leveraging the SOIPIX strategy of SOI-based monolithic sensor-electronics integration, applications are now being developed in areas such as medical (x-ray sensors and radiotherapeutic systems), materials research, nuclear physics, astrophysics, electron microscopy and industrial uses (such as x-ray inspection systems).

(Here at ASN, we covered the project and its implications for medical imaging back in 2010 – click here to read that piece.)

The next workshop, SOIPIX2015, will take place at Tohoku University (Sendai, Japan) 3-5 June 2015. Registration has been extended until 22 May 2015. Click here for registration information.

 *KEK is Japan’s High Energy Accelerator Research Organization.

Freescale’s Next-Gen IoT Microprocessor Will Be On 28nm FD-SOI (EETimes)

Freescale is designing its next generation microprocessor, the iMX7, on 28nm FD-SOI, EETimes has just revealed. This was in an article by Chief International Correspondent Junko Yoshida entitled Freescale, Cisco, Ciena Give Nod to FD-SOI (read it here). Freescale microcontroller SVP & GM Geoff Lees told EETimes the chip’s designed for “’secure’ IoT applications, including automotive (telematics, V2V, entry-level infotainment) and smart devices (healthcare, home appliances and factory automation)”. Samsung’s being tapped as the foundry. Cisco and Ciena are also using FD-SOI, the article stated.

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

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This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

Interview: Leti CEO Malier on the FD-SOI Breakthrough; Leti Days in Grenoble (24-26 June) & Semicon West

Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM.  Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.

To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.

ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news.  (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).

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Laurent Malier, CEO of CEA-Leti

Here are some excerpts from our conversation.

Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?

Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost.  In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology

 

ASN: In which areas did Leti contribute to FD-SOI development?

LM:  Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention.  Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.

Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.

 

ASN: Do you see opportunities for FD-SOI in IoT?

LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data.  You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise.  Look for more announcements coming up at Leti Days.

LetiDays2014

Kalray considers FD-SOI for many-core processors (Electronics360)

Kalray is considering an FD-SOI version of its family of programmable multicore processors, reports Peter Clarke of Electronics360 (see article here).  Clarke says that Kalray’s director of solutions and software services told him that while they’re currently on 28nm bulk, they’ve had customer interest in an FD-SOI version of a planned 64-core chip for telecom, automotive and medical apps.  The company says that its gigaflops-per-watt ratio is already one of the world’s best, and an FD-SOI version would make it even better.

Eveon and Leti Leverage SOI in Milestone: Fabrication Of Smart Bolus-type Micro-pump for Drug Delivery

Puce micropompe Flumin3

(Courtesy: CEA-Leti)

 

Eveon and CEA-Leti have demonstrated liquid-pumping for smart drug delivery in the bolus mode using a silicon-based micro-pump fabricated with a standard MEMS process. (Read full press release here.)

The milestone is the first functional micro-pump integration using MEMS standard process on Leti’s 200mm line. It is a result of FluMin3, Eveon and Leti’s three-year joint-development project to produce an automatic drug-delivery system integrating a MEMS micro-pump that reduces patient discomfort by delivering medicine with very high accuracy, minimal loss and high flow rates.

The micro-pump is based on core technology initiated by Eveon and IMEP-LAHC. The pump demonstrator is made from SOI wafers, which include a thin deformable membrane sealed over a fluidic cavity and fluidic valves determining inlet and outlet. A dedicated electromagnetic actuator developed by Cedrat Technologies shapes the membrane.

Debiotech expands target market for SOI-MEMS based solution to Type 2 diabetes

Debiotech_SOI_MEMS_ST

(Images courtesy: Debiotech)

Debiotech has debuted the JewelPUMP2, a new product dedicated to the Diabetes Type 2 market, based on Debiotech’s innovative JewelPUMP platform (press release here). By using its JewelPUMP platform, which is already in the industrialization phase and in preparation for the CE marking, Debiotech will be able to introduce the JewelPUMP2 shortly after its JewelPUMP for Type 1 patients, while ensuring the same degree of miniaturization, safety and reliability.

Back in 2009, Debiotech wrote in ASN (click here to read the article) about their Nanopump™, a volumetric membrane pump, at the heart of their systems. Co-designed by Debiotech and ST, and manufactured by ST, the pump consists of a membrane micromachined in an SOI wafer, which is in turn sandwiched between two Pyrex™ plates with throughholes. A piezoelectric actuator moves the membrane to compress and decompress the fluid in the pumping chamber.

Cambridge CMOS Sensors (CCMOS) says it is seeing increasing sales of its gas-sensing microsystems and is on the cusp of more major contracts.

Cambridge CMOS Sensors (CCMOS) says it is seeing increasing sales of its gas-sensing microsystems and is on the cusp of more major contracts. Gas-sensing technology has a broad range of applications, including domestic gas detectors, industrial safety, explosive detection, medical diagnostics and environmental monitoring. A Cambridge University spin-off that recently raised an additional £4.5m, the company was just named “Start-up of the Year” by BusinessWeekly.

Its sensors use high-temperature tungsten MOSFET heaters embedded in an SOI membrane. These effectively form a micro-hotplate that heats the sensing material, allowing it to react with gas molecules. Crucially, CCMOS’ MOSFETs can be fabricated in a commercial SOI-CMOS process and therefore can be fully integrated with the associated drive/detection circuitry. The devices can be heated from room temperature to 700°C in a fraction of a second and have the ultra-low power consumption suitable for battery operation.