Tag Archive MEMS

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.

SOI Consortium Welcomes ASN News

Changes are afoot on the SOI Consortium website. You’ve seen our great new look. Now we have also brought Advanced Substrate News (known to most as ASN) into our fold.

ASN has been bringing you SOI-related news for over a decade now. Editor-in-Chief Adele Hars will continue leading the charge, working closely with the Consortium’s expanding membership base to bring you key news and fresh perspectives from our industry.

The SOI ecosystem is kicking off a banner year in 2017. For example, we just got the news (read more here) that Consortium member GF is teaming up with Chengdu municipality in China on a new fab offering 22FDX, GF’s 22nm FD-SOI process technology. GF is also expanding Dresden’s capacity by 40 percent and augmenting their Singapore fab’s RF-SOI.

That’s just the tip of the iceberg. Watch these pages for more news from our members and the greater ecosystem (if you’re not yet signed up for our email alerts, please take a moment to fill in the form here). In addition to FD-SOI and RF-SOI, we’ll be further expanding our coverage of other fields leveraging SOI such as MEMS, photonics, power and more.

The Consortium will of course continue offering our extremely successful workshops and training sessions (April in Silicon Valley, June in Tokyo, September in Shanghai plus events in Europe TBA). If you can’t get there yourself, don’t worry. ASN will bring you up-close coverage of these events.

And finally, 2017 marks the 10th anniversary of the founding of the SOI Industry Consortium. We thank you all for your decade of support, and welcome your participation. (If your company is not yet a member, click here to learn more about how to join.)  

The SOI ecosystem is more dynamic than ever. Of course we still have plenty of work to do, and we look forward to sharing Consortium and ecosystem successes (and challenges!) with you here at ASN’s new home. We’d love to hear from you – and if you have an idea for a contributed article, please drop Adele an email.

Many thanks. Here’s to the beginning of a dynamic new partnership between the SOI Industry Consortium and ASN.

With best regards,

Carlos Mazure and Giorgio Cesana

Executive Directors

SOI Industry Consortium

 

Reminder re: top SOI Conference – IEEE S3S ’16 (SOI/3D/SubVt) CFP deadline April 15th. Keynotes: NXP, Skyworks, Qualcomm

S3SconflogoDon’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.

As of this writing, the following keynote speakers have been confirmed:

  • Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
  • Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
  • Nick Yu, Qualcomm : topic TBAieee_logo_mb_tagline

Invited speakers include:

  • Jamie Schaffer, GlobalFoundries : topic TBA
  • Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
  • Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
  • Xavier Garros, CEA-Leti : “Reliability of FDSOI”

As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.

Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :

  • SOI
  • 3D Integration
  • Subthreshold MicroelectronicsEDS-Logo-Reflex-Blue-e1435737971222

For current information on the conference visit the S3S website at: http://s3sconference.org/

LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.

Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

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Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

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Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

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Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

IEEE S3S, Top SOI/3D/SubVt Conference, Issues Call for Papers. Theme: Energy Efficient Tech for IoT. (Best Student Paper wins $1000)

ieee_logo_mb_taglineEDS Logo PMS3015_revu_smallThe IEEE S3S (SOI/3D/SubVt) has issued its call for papers for the 2016 conference (click here for details). The theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”. This industry-wide event gathers together widely known experts, contributed papers and invited talks focused on SOI Technology, Low-Voltage Devices/Circuits/Architectures, and 3D Integration. In addition to over 100 contributed and invited papers, the conference will feature prestigious Keynotes and a Hot Topics session.

logo_soiconsortiumFor the first time, the Conference will include two Tutorials free-of-charge with Conference registration: one on FD-SOI Circuit Design and another on Technologies for Monolithic 3D Integration. A full-day short course addresses Energy Efficient Computing and Communications including RF circuit technology.

The paper submission deadline is the 15th of April 2016. As always, there will be a Best Paper Award and a Best Student Paper Award. But for the first time, the Best Student Paper Award includes a $1,000 prize from one of the conference’s industry sponsors.

The papers presented here give industry an excellent window on what’s coming next. For example, work demonstrating a viable integration path for stacked nanowires that was first presented in a Leti paper at the 2015 S3S Conference was awarded the Paul Rappaport IEEE Prize two months later at IEDM 2015.

S3S is a great conference – don’t miss it.

Interview: Leti Is the Moving Force Behind FD-SOI. CEO Marie Semeria Explains the Strategy (part 1 of 2)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

MarieSemeria_LetiCEO_©PIERREJAYET

Marie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

Minatec_aerial_lores

Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

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Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

Click here to read part 2 of this exclusive interview.

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.

Advanced substrates for 3D and other new markets drive new fab inspection equipment – interview with Altatech GM

New approaches in chipmaking and fast-evolving specialty markets are driving the need for new equipment on the fab floor. 3D chips (be they stacked or bonded), MEMS, lighting, power – they’re all leveraging wafer substrates in new ways. Altatech, the equipment division of SOI-wafer leader Soitec, has just announced new inspection equipment for foundry and IDM customers fabbing 3D and other chips. ASN talks to Jean-Luc Delcarri, Altatech general manager, about the company and its recent announcements.

Advanced Substrate News (ASN): Can you tell us briefly about the company and the markets it serves?

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Jean-Luc Delcarri, Altatech general manager

Jean-Luc Delcarri (JLD): Altatech makes specialty equipment for the fab floor. We have two main areas of deep expertise: one is in defect inspection, and the other is in CVD* technologies for semiconductor, LEDs, MEMS and photovoltaic devices. I founded the company in 2004, and then in 2012 we became a subsidiary of SOI wafer leader, Soitec.

ASN: At Semicon Europa 2015, you announced “…a new, high-speed inspection system for ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS and mobile technologies.” What’s driving that market?

JLP: Yes, at Semicon we announced the Eclipse TS, which is a unique, high-reliability and easy-to-implement inspection system solution that’s now ready for mass production.

You’ve got the need for these advanced substrates that’s being driven by really rapidly growing markets in automotive, industrial power and mobile electronics. We’ve been working quietly on this tool for years, and now the Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer, so we’re really excited about it.

AltatechEclipseTSInspectionSystem2015

Altatech’s Eclipse TS, a high-speed inspection system for ultra-thin substrates in 3D applications.

ASN: What makes the Eclipse TS different from other inspection sytems?

JLP: When you’re looking for defects on these advanced wafer solutions, you have to do much more than scan the top: you need to inspect the front side, the back side and the edge of very thin wafers – and you have to do it without touching them. Our ability to do all this makes us totally unique on the market: we have built this tool on a strong IP portfolio.

So with the Eclipse TS, you have a high-speed inspection system that can measure very thin and stacked wafers down to 50 microns, as well as Taiko rings, stacked substrates and silicon-on-glass wafers. Plus we can do the front-side, back-side and edge inspection in one pass with no back-side contact.

In today’s 3D technologies, substrates undergo grinding, stacking and gluing, so you can end up with wafers with a very high bow, or  wafers with a warp of up to 6 mm. We can handle those wafers. In fact, the Eclipse system can monitor these sorts of processes. The inspection occurs without any contact on the active surface, and at a throughout of more than 90 wafers per hour for 300-mm substrates.

We’re of course compliant with the latest automation standards, so the system can be fully integrated into the line, and provide comprehensive reporting for defects classification and yield maps.

Our full Altatech Eclipse series covers advanced metrology and holistic inspection systems. That means we can detect, count and bin defects during the wafer manufacturing process as well as do continuous outgoing wafer-quality inspection. So the quality of both the wafer-surface and edge is ensured. We also have proprietary Eclipse sub-modules that detect specific sorts of particles and defects of interest for both patterned or unpatterned wafers.

All that puts Altatech in a leading position in what is a very large market opportunity.

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Altatech’s AltaCVD 3D Memory Cell deposits the ultra-thin semiconductor films used in high-density, low-power memory chips 10 times faster than conventional ALD systems.

ASN: You also make CVD – deposition – equipment. Can you tell us a little about that, and what’s driving those markets?

JLP: Sure. Last year we introduced the AltaCVD 3D Memory Cell™, which is the newest member of our AltaCVD product line. This is used for depositing ultra-thin semiconductor films when you’re manufacturing the high-density, low-power memory chips used throughout mobile electronics. Our new system does atomic-layer deposition 10 times faster than conventional ALD** systems, which is of course huge when you’re manufacturing advanced memories where you need to run in very high-volume production with extreme cost efficiency.

In the new 3D device architectures for mobile apps, our customers are looking to really increase memory capacity and boost performance. And to do this, they need very advanced material deposition to create atomic-layer films with high uniformity – you really are at the atomic level of control here. The AltaCVD 3D Memory Cell deposits layers of chalcogenide*** materials by using a combination of precursors, which is very leading edge.

So with our tool you can use conventional gaseous or solid precursors, but we also have a patented pulsed technology, which means you can also use advanced CVD precursors that are available only in liquid form. This is remarkable versatility: it allows us to achieve exceptional step coverage over features with very high aspect ratios – that’s a key performance requirement when you’re talking about vertical integration high-density memory circuits.

You can also use it for advanced pre-treatment of semiconductor surfaces (which improves circuit functionality), as well as post-treatment of surfaces (which enhances electrical performance).

Because it’s used in everything from research to high-volume manufacturing, it can process 200-mm or 300-mm substrates, and uses a single-wafer, multi-chamber architecture. One of our key customers demonstrated it last year. We’re now selling production units, and we’re pleased to say it’s been very successful.

ASN: Do you have other products in the pipeline?

JLP: Next up we have a new solution for high aspect ratio 3D copper deposition. The system, which is called RUBY, can deposit a barrier layer of titanium nitride or tantalum nitride with almost 100% step coverage on an aspect ratio higher than 10:1. This is followed by deposition of a copper seed layer with similar performance. Combined with a proprietary copper cleaning process, it will be able to meet the growing challenge of copper metallization in MEMS and semiconductor 3D integration. We’ll release it as soon as we’ve completed our product milestones for reliability and performance.

ASN: Where do you see the highest-growth areas?

JLP: We’ve developed the right technology for the right time in a number of key markets, so we’re really well-positioned to answer the needs of a number of high-growth markets. The move to 450mm wafers is something we’re ready for, which will probably happen first in advanced memories. But in the meantime we also see significant activity in MEMS, RF, high power and LEDs. We’re winning customers in China who are looking to be leaders in these markets. All in all, much of the future of the phone in your pocket depends on what we can help our customers do in high-volume and cost-effectively on the fab floor – so it’s a very exciting time to be in this business.

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*CVD=chemical vapor deposition

**ALD=atomic layer deposition

*** chalcogenides include sulphides, selenides, and tellurides

Need an Extra Day of Battery Life? Consider SiTime’s SOI-MEMS Timing Solutions (Planet Analog)

Using SiTimes’ SOI-MEMS based oscillator can extend battery life by a full day in some apps, Piyush Sevalia, Executive Vice President, Marketing for SiTime explained in a recent Planet Analog piece (read the whole thing here).

The traditional timing device is a quartz (passive crystal) resonator, which doesn’t draw any power itself. But it doesn’t save any either. As Piyush describes:

In a portable audio application for example, a SiT8021 oscillator operating at 3.072 MHz draws only 60 μ A compared to a quartz oscillator at 2.5 mA. In this case, the power consumption is 98% lower. This can effectively extend battery life by a full day – a huge improvement.

SiTime is a Bosch spin-off that’s now part of Megachips Corporation. The SiTime CTO first described their SOI-MEMS fabrication technology for ASN back in 2009 (read that here). Since then, they’ve shipped more than 300 million devices and captured 80% market share. Click here for more about SiTime’s SOI-MEMS solutions in ASN.

Industry 1st: Leti Demos MEMS on 300mm Wafers – And Yes, They’re SOI

In what may be a first for the MEMS industry, CEA-Leti has manufactured micro-accelerometers on 300mm wafers, a development that could lead to significantly lower MEMS manufacturing costs. And yes, those 300mm wafers are SOI wafers. These are “thick” SOI wafers, with an insulating BOx (buried oxide) layer of 2µm, and top silicon of 220nm.

The most advanced of Leti’s platforms is its M&NEMS technology based on detection by piezo-resistive silicon nanowires, which reduce sensor size and improve performances of multi-axis sensors. Leti’s inertial-sensor manufacturing concept enables the design and fabrication of combo sensors, such as three-axis accelerometers, three-axis gyroscopes and three-axis magnetometers on the same chip. This is a key component for IoT apps.

Leti’s M&NEMS concept, developed with 200mm technology, is currently being transferred to an industrial partner. Demonstration of this technology on 300mm wafers has shown very promising results.

In addition to lowering costs, manufacturing MEMS with 300mm technology enables 3D integration using MEMS CMOS processes in more advanced nodes than on 200mm, and the use of 3D through-silicon-vias (TSV), which is already available in 300mm technology. (Read the full Leti press release here.)