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ByGianni PRATA

Interview: Leti CEO Laurent Malier on FD-SOI and more

CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s future.  ASN had a chance to catch up with CEO Laurent Malier to see what’s up and what’s next.


Laurent Malier, CEO of CEA-Leti and President of the Association of Carnot Institutes

Advanced Substrate News: For those who don’t know Leti well, can you give us a general introduction, and tell us how you work with industry?

Laurent Malier: Leti focuses on micro- and nano-technologies and their applications. Our goal is to create innovation in those domains and transfer it to industry. We are part of the CEA, a French government-funded technological research organization. Seventy-five percent our 250M€ budget comes from industrial contracts.


Since we cover everything from silicon to applications, Leti addresses microelectronics, embedded software and applications in consumer, automotive, health-care, environment, space, safety and security, wireless and smart-devices markets.



Leti has worked with more than 365 industrial partners worldwide through one-to-one  collaborations, collaborative projects and common labs. We provide access to advanced technology platforms (we have 8,000m² of cleanroom space) and offer broad scientific and technological support.

ASN: Can you give us a bit of history on Leti’s role in SOI in general, and FD-SOI in particular?

LM: Leti has been involved in SOI since the early days with Leti researcher Michel Bruel’s original patent on the Smart Cut™ technology for manufacturing SOI wafers. That was in 1991, and the technology was licensed to Soitec in 1992. Leti’s active involvement in advanced on-oxide substrates development has continued since then. We have also been a pioneer in SOI-focused compact modeling. A Leti spin-off company called Soisic was created in 2001 and later bought by ARM to offer SOI-based design.

Last December, Leti announced Leti-UTSOI2, the first complete compact model for FDSOI. It enlarges the physically described bias range for designers and is available in all major SPICE simulators.

For wireless markets, Leti has taken part in the development of RF-SOI for 130 and 65nm from high-resistivity wafers and process integration to models.

Leti’s current SOI knowledge starts with the substrate, embraces the device and extends to the full design platform with TCAD support, compact modeling and design and conception.

Our strong focus on SOI devices and technology has produced original breakthroughs, ranging from the demonstration of interest in thin BOX substrate to multi-Vt design, and benefits from built-in power-performance trade-off tuning capabilities.


(Full PDF available here.)

ASN: Can you tell us more about Leti’s current and future contributions to FD-SOI?

LM: Fostered by Grenoble’s unique ecosystem, where substrate suppliers are located near IDMs and design companies, Leti’s work spans the whole range of activities related to SOI. Leti’s current contribution to FD-SOI covers the full spectrum: materials, process, integration, device, modeling, architecture and systems.


Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

Combining research and manufacturing experience, from a digital point of view, Leti supports 28nm FD-SOI at STMicroelectronics with an on-site team of more than 60 people. Leti has been part of the IBM Alliance based in Albany, NY since 2008. We’ve played a key role in 14nm FD-SOI development, with teams based in Albany, Grenoble and Crolles.

And more than anybody, Leti is now shaping 10nm FD-SOI. That’s what we do: we are always working well ahead of the industry!

In summary, Leti serves the global SOI ecosystem.

ASN: Can you give us a peak at Leti’s work on future devices, structures, substrates and so forth?

LM: With respect to10nm FD-SOI, Leti is currently addressing two main challenges. The first is how to implement performance boosters; and then how to optimize the smart use of back biasing to keep on leveraging SOI technology’s big competitive advantage in energy efficiency.

And what will be the next device? Definitely it will have to enable energy-efficient circuits. The race to lower overall energy consumption at no performance penalty has begun. Within this context, Leti is actively preparing the for future by evaluating potential scaled SOI architectures. Trigate, nanowires and stacked nanowires are options envisioned to pursue SOI CMOS-based scaling. Leti is also thoroughly investigating new device concepts to combine better performance with more energy-efficient hybrid circuits.

Leveraging our SOI expertise, Leti is paving the way to enable the 3D monolithic integration where layers of transistors are stacked with a lithographic alignment resolution: it allows connecting active areas at the transistor level. This revolutionary way of thinking about next nodes enables less consumption with better performance and is a unique technological tool to enable III-V and high mobility materials hybrid integration.

ASN: Will we see more Leti spin-offs?

LM: Most definitely. One of Leti’s goals is to foster the creation of startups that leverage our technological innovations. That creates jobs and value in the local economy, and opportunities for the electronics industry, globally. Leti is one of the world’s leading research institutions for startup creation: Soitec, Sofradir, ULIS, Movea, APIX Technology and Aledia are some of the companies that Leti has launched over the years.

We certainly intend to step up the pace. Last year, our recently revamped startup program launched Wavelens, which delivers compact MEMS-based optical solutions for the mobile phone market, and Primo1D, the ‘E-Thread®’, company. And ISKN, one of our currently incubated companies, had one of the most successful Kickstarter campaigns last year. It raised close to $350,000, almost 10 times its original goal, for iSketchnote, its smart iPad cover. So I think we can say there will be more Leti startups in the months and years to come.


Leti: Adding Strain to FD-SOI for 20nm and Beyond

Work at Leti shows that strain is an effective booster for high-performance at future nodes.

The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.

Stressor options for FD-SOI technology

Figure 1: Stressor options for FD-SOI technology

As illustrated in Figure 1, strain can be incorporated at various places in the transistor:

  • In the channel through the use of c-SiGe for PMOS devices and strained SOI (sSOI) material for NMOS.
  • In the source and drain region with the use of SiGe or SiC for P and NMOS respectively.
  • In the Middle-of-Line process with the deposition of tensile or compressive Contact Etch Stop Layers (t- or c-CESL).

First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si[1].

We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.

For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors[2] [1]. Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL[3] for NMOS and with rotated substrates[2], e-SiGe[4], SiGe channels[5] and (110) substrates[6] for pMOS.

For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost[1] and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel)[4]. Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).

Efficiency of stressor techniques for N & PMOS

Figure 2: Efficiency of stressor techniques for N & PMOS


In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.

NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.

– – – – –


[1] C. Fenouillet-Beranger, L. Pham Nguyen, P. Perreau, S. Denorme, F. Andrieu, O. Faynot, L. Tosti, L. Brevard, C. Buj, O.Weber, C. Gallon, V. Fiori, F. Boeuf, S. Cristoloveanu,

T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.

[2] S. Baudot, F. Andrieu, O. Faynot, J. Eymery, “Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator

(sSOI)”, Solid State Electronics, 2010.

[3] F. Andrieu, C. Fenouillet-Beranger, O. Weber, S. Baudot, C. Buj, J.-P. Noel, O. Thomas, O. Rozeau, P. Perreau, L. Tosti, L. Brevard, O. Faynot, “Ultrathin Body and BOX SOI

and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.

[4] S. Baudot, F. Andrieu, O. Weber, P. Perreau, J.F. Damlencourt, S. Barnola, T. Salvetat, L. Tosti, L. Brévard, D. Lafond, J. Eymery, O. Faynot, “Fully-Depleted Strained Silicon-

On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.

[5] F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,

A. Vandooren, B. Ghyselen, C. Mazure, N. Kernevez, G. Ghibaudo and S. Deleonibus, “Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with

HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.

[6] T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, S. Takagi, ”(110)-Surface Strained-SOI CMOS Devices”, IEEE Transaction of Electron Devices, 52, 3, p.367, 2005.


ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.

From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec):

“ FD-SOI Executive Summary

Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too.

At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors.

Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer.

Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments. ”

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

ST Technology Overview

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section):

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    – further improved electrostatic control and relaxed thinness requirement of the top silicon,

    – enables back-biasing through the BOX,

    – enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    – brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that

the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)

speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)

Focus on SRAM: 
The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline

Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.


28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

ByGianni PRATA

FD-SOI Workshop in SF Follows ISSCC – Registration (Free!) Now Open

Workshop FDSOI San Francisco 2012

Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)

The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.

It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.

The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.

Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.

The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)

This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.

Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.

The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.

Here’s a preview of program – you won’t want to miss it.

7:30am Badge pick up & On-site registration
8:00am Breakfast
8:30am Introduction by Carlos Mazure (Soitec)
8:40am Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Design by Philippe Flatresse (ST Microelectronics)
9:10am Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Technology by Michel Haond (ST Microelectronics)
9:40am Recent Advances in FDSOI by Bruce Doris (IBM)
10:10am Coffee Break
10:30am Library and Physical IP Porting for FDSOI by Jean-Luc Pelloie (ARM)
11:00am 20nm FDSOI Models by Brian Chen (Accelicon & SOI Consortium)
11:30am FinFET on SOI by Terrence Hook (IBM)
12:00pm Lunch
1:00pm Enabling Substrate Technology for a Large Volume Fully Depleted Standard by Christophe Maleville (Soitec)
1:30pm Strain Options for FDSOI by Olivier Faynot (CEA – Leti)
2:00pm Advanced FDSOI Design by Bora Nikolic (UC Berkeley)
2:20pm Closing Remarks by Horacio Mendez (SOI Consortium)
2:30pm Networking and coffee buffet

Right Timing

ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.

Input signal testing first and second switch delays starting from DCO or DC1.

SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).

ARM has recently developed new methodology(1) to validate the timing verification for SOI-based chips, and is currently working with foundry clients to tune their SPICE models accordingly.

To maximize accuracy, partially-depleted (PD) SOI timing verification must take into account the “history effect”, wherein the body voltage of a transistor is a function of its recent on/off history. While early SOI adopters had to deal with this on their own, for today’s designers the history effect is just another “corner” accounted for in the physical IP libraries, making it essentially transparent in the design flow.

We have done the work behind the scenes to ensure that both the foundries and fabless designers have models in which they can be completely confident.

Measured and SPICE simulated first switch inverter chain delay.

In the library

For standard cell libraries, ARM characterizes and incorporates timing verification in the library (.lib) files. SOI design requires two libraries per process-voltage-temperature (PVT) corner (whereas bulk silicon design uses one library per corner). For each function, a Max-SOI is characterized for the slowest operation possible, while a Min-SOI library is characterized for the fastest possible operation due to the history effect. The timing analysis tool uses these libraries.

However, it’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.

ARM has developed and proven this reliable timing verification methodology on a 45nm SOI standard cell library. This methodology, which can be applied to any cell, also enables our foundry customers to fine tune their SPICE models, dissociating NMOS from PMOS (rise/fall transition). The same methodology is applied to the 32 and 22nm nodes.


The methodology uses both floating-body (FB) and body-contacted (BC) cells (which should not have any history effect at all). It extracts the history effect delay chain timing measurements. Three types of delay chains (FB/FB, BC/BC and FB/BC) are implemented, measured, simulated and compared with a foundry’s actual silicon results.

Essentially, we measure the chain delay of the rise and fall transistions, for the two first switches corresponding to DC0 and DC1 conditions known to deliver the worst case history effect in most cases. We also measure the delays when the steady-state is reached after the signal has been toggling for a long time (typically a few ms).

The measurements are then compared to SPICE simulation results.

Measured and SPICE simulated history effect for rise transition on inverter chain.


Taking one foundry’s BC/BC delay chain as an example, cumulated measurements indicated that 95% of the measurements had a better than 2% accuracy and that the BC chain was exempt of history effect as expected. The silicon measurements were found to be close to the simulation results using the typical process corner. They indicated that the temperature inversion point was close to 0.8V.

A good correlation was obtained between the FB/FB and the FB/BC extracted history effect. However, the simulated history effect spread more than the measured one, which indicated that the SPICE models needed to be retuned to be more accurate in the history effect prediction and then avoid too much pessimism.

ARM helped the foundry retune the SPICE models for greater accuracy. The same methodology has now been used for modeling at the 32nm and 22nm nodes, and for fast and slow process corners.

[1] JL Pelloie et al. Timing Verification of a 45nm SOI Standard-Cell Library. IEEE SOI Conference 2010.