CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s future. ASN had a chance to catch up with CEO Laurent Malier to see what’s up and what’s next.
Laurent Malier, CEO of CEA-Leti and President of the Association of Carnot Institutes
Advanced Substrate News: For those who don’t know Leti well, can you give us a general introduction, and tell us how you work with industry?
Laurent Malier: Leti focuses on micro- and nano-technologies and their applications. Our goal is to create innovation in those domains and transfer it to industry. We are part of the CEA, a French government-funded technological research organization. Seventy-five percent our 250M€ budget comes from industrial contracts.
Since we cover everything from silicon to applications, Leti addresses microelectronics, embedded software and applications in consumer, automotive, health-care, environment, space, safety and security, wireless and smart-devices markets.
Leti has worked with more than 365 industrial partners worldwide through one-to-one collaborations, collaborative projects and common labs. We provide access to advanced technology platforms (we have 8,000m² of cleanroom space) and offer broad scientific and technological support.
ASN: Can you give us a bit of history on Leti’s role in SOI in general, and FD-SOI in particular?
LM: Leti has been involved in SOI since the early days with Leti researcher Michel Bruel’s original patent on the Smart Cut™ technology for manufacturing SOI wafers. That was in 1991, and the technology was licensed to Soitec in 1992. Leti’s active involvement in advanced on-oxide substrates development has continued since then. We have also been a pioneer in SOI-focused compact modeling. A Leti spin-off company called Soisic was created in 2001 and later bought by ARM to offer SOI-based design.
Last December, Leti announced Leti-UTSOI2, the first complete compact model for FDSOI. It enlarges the physically described bias range for designers and is available in all major SPICE simulators.
For wireless markets, Leti has taken part in the development of RF-SOI for 130 and 65nm from high-resistivity wafers and process integration to models.
Leti’s current SOI knowledge starts with the substrate, embraces the device and extends to the full design platform with TCAD support, compact modeling and design and conception.
Our strong focus on SOI devices and technology has produced original breakthroughs, ranging from the demonstration of interest in thin BOX substrate to multi-Vt design, and benefits from built-in power-performance trade-off tuning capabilities.
(Full PDF available here.)
ASN: Can you tell us more about Leti’s current and future contributions to FD-SOI?
LM: Fostered by Grenoble’s unique ecosystem, where substrate suppliers are located near IDMs and design companies, Leti’s work spans the whole range of activities related to SOI. Leti’s current contribution to FD-SOI covers the full spectrum: materials, process, integration, device, modeling, architecture and systems.
Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)
Combining research and manufacturing experience, from a digital point of view, Leti supports 28nm FD-SOI at STMicroelectronics with an on-site team of more than 60 people. Leti has been part of the IBM Alliance based in Albany, NY since 2008. We’ve played a key role in 14nm FD-SOI development, with teams based in Albany, Grenoble and Crolles.
And more than anybody, Leti is now shaping 10nm FD-SOI. That’s what we do: we are always working well ahead of the industry!
In summary, Leti serves the global SOI ecosystem.
ASN: Can you give us a peak at Leti’s work on future devices, structures, substrates and so forth?
LM: With respect to10nm FD-SOI, Leti is currently addressing two main challenges. The first is how to implement performance boosters; and then how to optimize the smart use of back biasing to keep on leveraging SOI technology’s big competitive advantage in energy efficiency.
And what will be the next device? Definitely it will have to enable energy-efficient circuits. The race to lower overall energy consumption at no performance penalty has begun. Within this context, Leti is actively preparing the for future by evaluating potential scaled SOI architectures. Trigate, nanowires and stacked nanowires are options envisioned to pursue SOI CMOS-based scaling. Leti is also thoroughly investigating new device concepts to combine better performance with more energy-efficient hybrid circuits.
Leveraging our SOI expertise, Leti is paving the way to enable the 3D monolithic integration where layers of transistors are stacked with a lithographic alignment resolution: it allows connecting active areas at the transistor level. This revolutionary way of thinking about next nodes enables less consumption with better performance and is a unique technological tool to enable III-V and high mobility materials hybrid integration.
ASN: Will we see more Leti spin-offs?
LM: Most definitely. One of Leti’s goals is to foster the creation of startups that leverage our technological innovations. That creates jobs and value in the local economy, and opportunities for the electronics industry, globally. Leti is one of the world’s leading research institutions for startup creation: Soitec, Sofradir, ULIS, Movea, APIX Technology and Aledia are some of the companies that Leti has launched over the years.
We certainly intend to step up the pace. Last year, our recently revamped startup program launched Wavelens, which delivers compact MEMS-based optical solutions for the mobile phone market, and Primo1D, the ‘E-Thread®’, company. And ISKN, one of our currently incubated companies, had one of the most successful Kickstarter campaigns last year. It raised close to $350,000, almost 10 times its original goal, for iSketchnote, its smart iPad cover. So I think we can say there will be more Leti startups in the months and years to come.
Work at Leti shows that strain is an effective booster for high-performance at future nodes.
The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past.
As illustrated in Figure 1, strain can be incorporated at various places in the transistor:
First, it is worth noting that local stressors are often more effective on FD-SOI than on bulk at a given geometry because of the mechanical properties of the buried SiO2, which is less stiff than Si.
We have assessed different boosters on the FD-SOI architecture. The results are summarized in Figure 2.
For NMOS, one can see that sSOI is the more promising stressor with an ION improvement of 20-35 % for wide devices; and, it can increase up to 50 % for W = 50 nm narrow transistors . Our preliminary results let us predict a better scalability for sSOI than for t-CESL or SMT. Moreover, the compatibility of sSOI was already proved (even if the ION-boosts are not always totally additive) with t-CESL for NMOS and with rotated substrates, e-SiGe, SiGe channels and (110) substrates for pMOS.
For pMOSFETs, there are several options to enhance the ION, the simpler being the 45° rotated substrates with a 8 % boost and r-SiGe with a 18 % improvement by an access resistance reduction (37 % if a strain can also be generated into the channel). Once again, the scalability of the global boosters is certainly better than for the local ones (c-CESL and e-SiGe).
In conclusion, thanks to all the experiments already run, we are confident in the fact that strain can be incorporated in the planar FDSOI architecture, thus boosting performance even further at 20 nm and beyond.
NOTE: This article was adapted from the Leti presentation, “FD-SOI strain options for 20 nm and below”, given at the SOI Consortium’s 6th FD-SOI Workshop. The complete presentation is available at www.soiconsortium.org.
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T. Skotnicki, “Ultra compact FDSOI transistors (including Strain and orientation) processing and performance”, ECS Transaction, 2009.
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(sSOI)”, Solid State Electronics, 2010.
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and sSOI for Low Power Application at the 22 nm technology node and below”, invited talk at SSDM, 2009.
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On-Insulator p-MOSFETs with Recessed and Embedded Silicon-Germanium Source/Drain”, 2010.
 F. Andrieu, T. Ernst, O. Faynot, Y. Bogumilowicz, J.-M. Hartmann, J. Eymery, D. Lafond, Y.-M. Levaillant, C. Dupré, R. Powers, F. Fournel, C. Fenouillet-Beranger,
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HfO2 /TiN gate stack down to 15 nm gate length”, IEEE SOI Conference, p. 223-5, 2005.
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Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)
The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.
It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.
The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.
Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.
The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)
This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.
Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.
The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.
Here’s a preview of program – you won’t want to miss it.
|7:30am||Badge pick up & On-site registration|
|8:30am||Introduction by Carlos Mazure (Soitec)|
|8:40am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Design by Philippe Flatresse (ST Microelectronics)|
|9:10am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Technology by Michel Haond (ST Microelectronics)|
|9:40am||Recent Advances in FDSOI by Bruce Doris (IBM)|
|10:30am||Library and Physical IP Porting for FDSOI by Jean-Luc Pelloie (ARM)|
|11:00am||20nm FDSOI Models by Brian Chen (Accelicon & SOI Consortium)|
|11:30am||FinFET on SOI by Terrence Hook (IBM)|
|1:00pm||Enabling Substrate Technology for a Large Volume Fully Depleted Standard by Christophe Maleville (Soitec)|
|1:30pm||Strain Options for FDSOI by Olivier Faynot (CEA – Leti)|
|2:00pm||Advanced FDSOI Design by Bora Nikolic (UC Berkeley)|
|2:20pm||Closing Remarks by Horacio Mendez (SOI Consortium)|
|2:30pm||Networking and coffee buffet|
ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
ARM has recently developed new methodology(1) to validate the timing verification for SOI-based chips, and is currently working with foundry clients to tune their SPICE models accordingly.
To maximize accuracy, partially-depleted (PD) SOI timing verification must take into account the “history effect”, wherein the body voltage of a transistor is a function of its recent on/off history. While early SOI adopters had to deal with this on their own, for today’s designers the history effect is just another “corner” accounted for in the physical IP libraries, making it essentially transparent in the design flow.
We have done the work behind the scenes to ensure that both the foundries and fabless designers have models in which they can be completely confident.
For standard cell libraries, ARM characterizes and incorporates timing verification in the library (.lib) files. SOI design requires two libraries per process-voltage-temperature (PVT) corner (whereas bulk silicon design uses one library per corner). For each function, a Max-SOI is characterized for the slowest operation possible, while a Min-SOI library is characterized for the fastest possible operation due to the history effect. The timing analysis tool uses these libraries.
However, it’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.
ARM has developed and proven this reliable timing verification methodology on a 45nm SOI standard cell library. This methodology, which can be applied to any cell, also enables our foundry customers to fine tune their SPICE models, dissociating NMOS from PMOS (rise/fall transition). The same methodology is applied to the 32 and 22nm nodes.
The methodology uses both floating-body (FB) and body-contacted (BC) cells (which should not have any history effect at all). It extracts the history effect delay chain timing measurements. Three types of delay chains (FB/FB, BC/BC and FB/BC) are implemented, measured, simulated and compared with a foundry’s actual silicon results.
Essentially, we measure the chain delay of the rise and fall transistions, for the two first switches corresponding to DC0 and DC1 conditions known to deliver the worst case history effect in most cases. We also measure the delays when the steady-state is reached after the signal has been toggling for a long time (typically a few ms).
The measurements are then compared to SPICE simulation results.
Taking one foundry’s BC/BC delay chain as an example, cumulated measurements indicated that 95% of the measurements had a better than 2% accuracy and that the BC chain was exempt of history effect as expected. The silicon measurements were found to be close to the simulation results using the typical process corner. They indicated that the temperature inversion point was close to 0.8V.
A good correlation was obtained between the FB/FB and the FB/BC extracted history effect. However, the simulated history effect spread more than the measured one, which indicated that the SPICE models needed to be retuned to be more accurate in the history effect prediction and then avoid too much pessimism.
ARM helped the foundry retune the SPICE models for greater accuracy. The same methodology has now been used for modeling at the 32nm and 22nm nodes, and for fast and slow process corners.
 JL Pelloie et al. Timing Verification of a 45nm SOI Standard-Cell Library. IEEE SOI Conference 2010.