Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) – which was just a year after they had announced mass production of 28FDS process technology.
At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology.
Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry’s current and future demands especially in consumer, IoT and automotive applications.
In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”
Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI.
At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety).
Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe’s largest independent IC design consultancy.)
In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows.
For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.
And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP & GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D & 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.
In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.)
This is leading to some really nice wins for NXP. For example, they’ve got Amazon’s Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.
Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”.
As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.
2019 will be a busy fall for the SOI Consortium and our members.
First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates & locations locked in, so you’ll want to mark your calendars:
The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany.
The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.
Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website.
You’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration.
Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.
And finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including:
If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below.
IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality.
All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.
Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.
Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.
It’s a great program:
1:00pm – Welcome by Semi
1:10pm – IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP
1:35pm – The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials
2:00pm – The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries
2:25pm – Engineered Substrates – Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec
2:50pm – Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG
3:15pm – Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:
4:05pm – Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium
4:20pm – End
This is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!
And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R&D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.
Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)
At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.
Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.
The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.
We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.
Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot.
Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available – click here to get them.
The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.
NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.
The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D & 3D graphics they need for wearables and portables in consumer and industrial applications.
Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.
Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.
Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard…it’s amazing.”
FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.
In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).
Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.
FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).
Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it’s 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.
Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.
Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).
Kelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers.
At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML.
There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.
Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!
That’s all for this post. The next post — part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave — is now available. Click here to read on.
It should be a good year across the SOI ecosystem, with new products, players, IP, technologies and tools — and high volumes.
What’s new? Let’s start with the people, as the Consortium welcomes new team members. Jon Cheek of NXP will join Carlos Mazure as Executive Co-Director. He’ll be replacing ST’s Giorgio Cesana in that role – and goodness knows those are some big shoes to fill. Giorgio has given of his time and expertise so tirelessly over many years. He’ll of course still be a key resource for the SOI ecosystem, and though we’ll miss him here at the Consortium, we know he’ll be doing great things in SOI at ST. So a heartfelt thanks to Giorgio Cesana from all of us.
Jon Cheek has a long history in engineering management at companies that have been leading users of SOI: AMD, Freescale and now NXP. As such, he understands what companies need to design great products, and how the Consortium can help further build, promote, connect and support the ecosystem. The Consortium team also welcomes Jean-Eric Michallet of Leti, who’ll bring deep bizdev expertise and a keen sense of what it takes to reach further into the ecosystem. (Astute long-time ASN readers might remember his post from five years ago about 3D monolithic integration – now dubbed “Cool Cube” by Leti.) And finally, look to hear more from and about the Consortium, as our team is rounded out with the addition of the comm & marketing savvy of Erin Berard of Soitec.
In addition to new team members, the Consortium is very pleased to welcome new member Applied Materials. Though new to the Consortium, AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a consortium member is clearly a fabulous addition.
2019 will also be marked by the expansion of the highly successful SOI Academy series, the first of which was held this past fall in Shanghai. We’ll keep you posted as these and other Consortium events are announced throughout the year. In fact, 2019 marks a decade of (excellent!) SOI Consortium events events around the world: our first symposium was held back in 2009. Kicking off this year, save April 9th on your calendar for our Annual SOI Silicon Valley Symposium. Then watch this page for more events across the globe.
What will the year bring? On the product side, RF-SOI for 5G is of course super hot. Last summer, a SemiconductorEngineering headline proclaimed RF-SOI Wars Begin. And what we heard at the International RF-SOI Workshop last fall in Shanghai (presentations here) certainly confirmed that in the coming year the race will continue unabated.
And for FD-SOI, you might want to read the SE series published over the last six months. The latest, published a couple of weeks ago looks at FD-SOI at the Edge. There are some great insights from SOI Consortium members there. In terms of products, too, there’s lots of activity.
Last summer, Samsung indicated they’d taped out over 60 products since they first began offering 28FDS three years ago. It’s a trend they see accelerating. Full production of 18FDS is slated for this fall.
And also last summer GlobalFoundries indicated they had over 50 client designs on 22FDX. “We’re only just beginning,” said GF CEO Tom Caulfield at the time. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. ”
For its part, ST, as we learned at the last SOI Consortium Japan Workshop, has been doing FD-SOI for five years now. And while we don’t have number, we learned that some of those products are now in their second and third generations, and that some big FD-SOI chips coming out this year with embedded memory and RF, with especially good traction in mmWave, automotive and IoT.
So while the outlook for the overall industry is anyone’s guess for the coming year, the outlook for chips built on SOI technologies is very good indeed.
Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It’s in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance).
If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you’ll want to share this piece with them right away.
Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What’s more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don’t worry that this might be too technical: Sellier’s writing is thoroughly accessible (and engaging!) for anyone in the industry.
He starts with the wafer history, then quickly moves on to the features from the designer’s standpoint. And he puts it all in a business perspective. I can’t recommend this piece enough – even if you think you know everything already yourself, you’re sure to learn something new.
Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It’s that simple. That’s a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium’s 2018 SOI Symposium in Silicon Valley
The afternoon then featured presentations by foundry partners, which I’ll cover here.
Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I’ll cover those in Part 3 of this series.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it.
The presentations are starting to be posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here.
The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they’d consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design.
From a transistor viewpoint, the top reasons to choose FD-SOI is that it’s better for analog and has lower leakage/parastics. It’s perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave.
From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical.
With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company’s foundry business. FD-SOI, he continued, is on a “differentiation path.”
Samsung’s 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They’re seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks.
FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year.
The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.)
The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019.
With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF’s 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan.
Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it’s more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe.
Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they’re already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF’s requirements.
So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.