A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more.
Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore. It goes into SOI wafer technology, electrical properties, modeling, PD-SOI, FD-SOI, FinFETs and junctionless transistors, RF, ultralow-power, photonics, memory, power and MEMS. (See Table of Contents here.) This book should be a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics, as well as for electrical engineers in the automotive and consumer electronics sectors.
Silicon-On-Insulator (SOI) Technology, Manufacture and Applications is published by Woodhead Publishing, and is also available in print and ebook forms from major online retailers such as Amazon, Elsevier and Barnes & Noble. It was compiled and edited by Oleg Kononchuk, chief scientist at Soitec, France, and Bich-Yen Nguyen, a senior fellow at Soitec, USA.
By Ali Khakifirooz (Spansion)
One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward body bias (FBB) is available owing to oxide isolation and the use of flip-well structure .
While designers are familiar with the concept of body biasing and have been using it in different forms for many years in bulk CMOS technology, concerns are occasionally raised – often from non-designers – about the complexity and effectiveness of body biasing in advanced nodes.
Body biasing has been known for many years  and was in fact identified as a key technology enabler in sub-0.1µm era by industry leaders . Although ironically the recent move to the FinFET structure removed this gadget from the designers’ toolbox, the need for body biasing is still echoed .
Early studies demonstrated the effectiveness of body biasing in reducing leakage, improving performance, and reducing variability and thereby worst-case power consumption in complex circuits [5-7]. It was, however, pointed out that due to the competing effect of other leakage mechanisms, such as band-to-band tunneling, the effectiveness of reverse body bias (RBB) in managing leakage diminishes with technology scaling . Nonetheless Intel continued using body biasing at least down to 45nm node .
Static Body Biasing
Device variability is one of the key detractors of product yield. Historically, the desktop-driven semiconductor industry used product binning to turn this natural performance variability into profit. However, it is known that changes in market demand or process may lead to significant imbalance between the demand and inventory . Moreover, with the emergence of mobile applications as the dominant technology driver  and strict power requirements, binning is not effective anymore. With the desire to reduce VDD below 0.8V in order to reduce active power, managing the device variability becomes increasingly important.
Body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.
For example, in a media processor design in 65nm technology a 20% reduction in the worst-case delay was achieved by using an embedded FBB circuit . While most body biasing designs are geared toward keeping VT constant, it has been shown that a combination of VT and drive current control leads to significantly tighter distribution (an 85% reduction in variation) and 25% reduction in total power . These numbers are well comparable to the power saving expected from scaling the design by one technology node. Given the concerns about the saturation of cost scaling beyond 28nm, an FD-SOI design with a wide range of body biasing is thus very appealing.
Dynamic Body Biasing
For applications with varied workload, a more elaborate use of body bias is to adjust the transistor performance based on the workload. This can be, of course, combined with other known low-power techniques such as dynamic voltage and frequency scaling (DVFS), sleep transistors, power gating, etc. In particular, when combined with DVFS, the optimum VT for each VDD can be used to minimize total power .
Design Complexity and Area Overhead
Potentially added design complexity and area overhead due to body bias generation circuits and routing is sometimes voiced as a concern. Static body biasing is relatively easy to implement. Depending on the level of sophistication it requires some sensing circuits (leakage, delay, skew, temperature, etc.), charge pump circuits to generate the body bias, and a network to distribute it across the chip. In typical designs, this does not impose more than 1-2% area overhead. The design complexity is actually reduced as less resources are needed to meet target performance across process and temperature corners. Notable bulk CMOS designs that used body bias to reduce variability include Samsung’s ExynosTM SoC in both 32nm and 28nm node [13-14], and Oracle’s SPARC processors in 40nm .
Dynamic body biasing, on the other hand, needs additional system and software development. However, we do not expect this to be more complex than implementing any other low-power technique such as dynamic voltage scaling. An example is TI’s 45nm OMAP SoC that used body bias as a part of their SmartReflex technology (Figure 1) .
Figure 1. Example of combined dynamic body bias and voltage scaling in TI’s 45nm SoC . Proper VDD and body bias is selected based on the power mode and process corner. (Courtesy: ISSCC, TI)
No Body Effect?
While many bulk CMOS designs used body bias in some form, on the other end of the spectrum are the designs that used PD-SOI technology, where majority of the devices do not have a body contact. The lack of body effect in PD-SOI devices was claimed to help stacked transistors and passgates, leading to 15-25% speed improvement . For designers that prefer a zero-body-effect style, the move to FinFET or a thick BOX FD-SOI structure seems more natural. However, for mainstream applications where power and parametric yield are the main drivers, thin BOX FD-SOI and use of body bias is more sensible.
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 D. Jacquet, et al., “A 3 GHz dual core processor ARM CortexTM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization,” IEEE JSSC, p. 812, 2014.
 M. Kube, R. Hori, O. Minato, and K. Sato, “A threshold voltage controlling circuit for short channel MOS integrated circuits,” ISSCC, p. 54, 1976.
 S. Thompson, I. Young, J. Greason, and M. Bohr, “Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 µm logic designs,” Symp. VLSI Tech., p. 69, 1997.
 G. Yeap, “Smart mobile SoCs driving the semiconductor industry: technology trend, challenges and opportunities,” IEDM Tech. Dig., p. 1.3.1, 2013.
 M. Miyazaki, et al., “A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias,” ISSCC, p. 420, 2000.
 S. Narendra, et al., “1.1V 1GHz communication router with on-chip body bias in 150nm CMOS,” ISSCC, p. 218, 2002.
 J. Tchanz, et al., “Adaptive body bias for reducing impact of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” ISSCC, p. 422, 2002.
 A. Keshavarzi, et al., “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s,” ISLPED, p. 252, 1999.
 F. Hamzaoglu, et al., A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal-gate CMOS technology,” ISSCC, p. 376, 2008.
 J.Y. Chen, “GPU technology trends and future requirements,” IEDM Tech. Dig., p. 3, 2009.
 S. Nomura, et al., “A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology,” ISSCC, p. 262, 2008.
 M. Sumita, et al., “Mixed body-bias technique with fixed Vt and Ids generation circuits,” ISSCC, p. 158, 2004.
 S.-H. Yang, et al., “A 32nm high-k metal gate application processor with GHz multi-core CPU,” ISSCC, p. 214, 2012.
 Y. Shin, et al., “28nm high-k metal-gate heterogeneous quad-core CPUs for high-performance and energy efficient mobile application processor,” ISSCC, p. 154, 2013.
 J.L. Shin, et al., “A 40nm 16-core 128-thread CMT SPARC SoC processor,” ISSCC, p. 98, 2010.
 G. Gammie, et al., “A 45nm 3.5G baseband-and-multimedia application processor sing adaptive body-bias and ultra-low-power techniques, ISSCC, p. 258, 2008.
 M. Canada, et al., “A 580MHz RISC microprocessor in SOI,” ISSCC, p. 430, 1999.
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Good news for the SOI ecosystem: SOI wafer suppliers Soitec and SunEdison (formerly MEMC) have ended their longstanding legal feud and entered into a patent cross-license agreement (press release here). The agreement provides each company with access to the other’s patent portfolio for SOI technologies and ends all their outstanding legal disputes.
For Soitec, it represents a milestone for the SOI ecosystem, said Christophe Maleville, SVP of the company’s Digital Electronics Division.
For SunEdison, it adds to the company’s current SOI product capability, said Horacio Mendez, VP of the company’s Semiconductor Advanced Solutions division.
The agreement covers wafers for device architectures such as partially-depleted SOI (PD-SOI), fully-depleted SOI (FD-SOI) and radio-frequency SOI (RF-SOI) as well as advanced FinFETs.
The two companies have also agreed to grant each other the right to use their respective wholly-owned patents for research and development purposes. This applies to the development of products with advanced semiconductor materials beyond silicon that enable the fabrication of high-mobility channels for advanced generation digital applications.
For those new to FD-SOI, here’s a short description of the basic principles.
FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and processed wafer cost over Bulk transistor.
The major obstacles in scaling both the voltage and the transistor geometry are driven by manufacturing fluctuations. Fully Depleted SOI controls transistor fluctuations by nearly eliminating the variability due to channel-dopant distribution.
The objective of producing wafers with a thin Buried Oxide (BOX) is to enable back-bias. The back-bias is applied through a Well contact, etched through the BOX .With back-bias, the transistor Vt can be readily controlled by appliying voltage to the Well under the gate (fig1).
The advantage of impletmenting back-bias in FD SOI as opposed to Bulk is that the BOX acts as an isolation barrier for p-n juction leakage. The back bias can be controlled independently for the P and N transistors to optimize leakage and performance.
Publications by Hitachi’s Yamaoka et al, show that “by using a forward back-gate bias, Ion can be increased by about + 20%. While using a reverse back-gate bias, Ioff can be reduced by about up to 90%. Even if we apply some voltages to the back gate, the substrate current does not increase”. These measurements were made at 65nm. The advantages become even more acute at 20nm and below (see Figure 2).
These transistor advantages in FD SOI, provide significant advantages for mobile SoC’s.
|Target Markets||Mobile computing of all kinds: Games, smart phones, tablets, etc.|
|Power||Provides low power at handset class performance|
|Performance||Power/performance improves at lower voltage|
|Leakag||Lower leakage by design|
|Complexity||Simpler and cost-efficient manufacturing. This is particularly true when compared to 3-D transistors such as FinFETs|
|Design Compatibility||Fully compatible with bulk, no floating body effects to worry about|
For more in-depth information, see the white paper on the SOI Consortium website.
The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront.
As always, performance gains generate plenty of buzz. But the SOI papers were also notable for work reducing power consumption, extending scalability and overcoming threshold voltage variation.
IBM presented the world’s highest frequency microprocessor to date, clocking in at 5.2 GHz. On 45nm SOI, it’s the first commercial processor ever to break through the 5GHz speed barrier, and is the centerpiece of Big Blue’s new zEnterprise 196 system.
In another paper, IBM presented the first embedded high-k/metal-gate (HK/MG) SRAM on 32nm SOI enabling operation at down to 0.7V.
AMD presented its Bulldozer 2-core modules, which are on 32nm SOI with HK/MG. Clocking in at 3.5GHz, we’ll see them beginning in desktop and server Fusion chips this year.
In a quieter but clearly significant paper, ST and Leti compared 65nm low power (LP) partially depleted (PD) SOI with standard 65nm LP CMOS bulk. They found that PD-SOI, when combined with a low resistivity produced with forward body bias of the power switch, can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.
For summaries of additional SOI-based papers at ISSCC and other recent conferences, see ASN’s PaperLinks.
FD-SOI enables the use of a slightly different transistor structure than PD-SOI. Each has advantages and disadvantages. Here is a quick layman’s guide to the differences.
Partially depleted SOI has been successfully leveraged for high-performance microprocessors and most other SOI applications for almost a decade. Although OKI has used FD-SOI commercially for a long time, its focus has always been on niche ultra-low power applications. Now, the high-performance world is looking at advanced devices such as ultra-thin body FDSOI MOSFETs and multiple-gate MOSFETs (aka MuGFETs) as potential ways to drastically cut power consumption and leakage while preserving high performance and minimizing short channel effects, probably starting with the 22nm node. See the following graphic and table for an indication of the basic differences between PD and FD SOI.