CEA-Leti’s newest version of its advanced compact model for FD-SOI is now available in all major SPICE simulators (get the press release here). The Leti-UTSOI2.1 is the latest version of Leti’s compact model for FD-SOI, which was first released in 2013. (Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. )
Leti-UTSOI2.1 further improves predictability and accuracy. These improvements include a direct and predictive link between bi-dimensional device electrostatics and process parameters, a refined description of narrow-channel effects, improved accuracy of moderate inversion regime and gate tunneling current modeling.
“This new version of the ultra-thin SOI model, which affirms Leti’s continuing leadership in FD-SOI technology, is ideal for designers seeking differentiation in energy management and performance for advanced nodes,” said Leti CEO Marie-Noëlle Semeria
Leti-UTSOI2.1, which considerably extends the domain of physical device description compared to other solutions, is now available in most of the commercial SPICE and Fast SPICE simulators used by industry.
In his recent piece, A couple of misconceptions about FD-SOI (3 September 2014), semiwiki blogger and IP expert Eric Esteve corrects some assertions surfacing about FD-SOI. He reminds designers that to really benefit from FD-SOI, you want to leverage body-biasing. He explains how ST has automated the IP conversion process so it takes about half the time you’d normally expect. He also advocates FD-SOI for wearables and smartphones, as it provides both performance advantages and power savings.
The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.
First, let’s consider the markets we’re addressing.
The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.
Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.
It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.
The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.
FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.
FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.
In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.
The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.
The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.
This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.
With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.
FD-SOI: Competitive Positioning
To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.
Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)
Gate cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)
The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.
Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.
The gate cost of 20nm FD-SOI is 20% lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.
14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.
Why the hesitation in using FD-SOI?
While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.
Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.
FD-SOI for High-Volume Applications
The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).
To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:
At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.
The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.
Two important FD-SOI wins for STMicroelectronics have just been announced:
The Energy Technology Award was presented at a ceremony for the 2013 Annual Creativity in Electronics (ACE) Awards. It is given by EETimes and EDN, two of the most prominent trade-media sources in electronics. The ACE Awards honor the people and companies behind the technologies and products that are changing the world of electronics and shaping the way we work, live, and play.
Why the energy category? ST attribututes it to FD-SOI’s ability to reduce energy consumption and carbon emissions in two important ways. First, manufacturing FD-SOI is simpler and requires 15% fewer process steps than equivalent traditional silicon technologies and far less than complex alternatives to achieve similar performance, thereby using less energy per wafer produced. Moreover, products manufactured using FD-SOI technology show energy savings between 20 and 50%, making end-user devices run cooler and last longer.
Commenting on the award, Executive Vice President of Front-End Manufacturing & Process R&D, Digital Sector Joel Hartmann said, “The Energy Technology Award confirms that FD-SOI is a game-changing technology that addresses the low-power and high-performance needs of the market. It also empowers chipmakers to deliver products meeting the dual benchmark of industry-beating “performance per watt” and “performance per watt per dollar.”
And of course, ST’s FD-SOI is ready for manufacturing now: it’s a faster, simpler and cooler upgrade to traditional semiconductor manufacturing at process nodes of 28nm and below.
Which is why we’re now starting to hear about customers! Here’s what they had to say at their Q1 2013 Results – Earnings Call (the transcript was just posted on Seeking Alpha).
“In Digital Convergence, I’m pleased to say we earned important design wins in the FD-SOI advanced CMOS technology, the next-generation process technology that ST is pioneering,” said Carlo Bozotti, Chairman of the ST Managing Board, CEO and President in his opening remarks.
In a follow-up question from a BNP Paribas analyst, he added, “On the FD-SOI, we are working very aggressively on two fronts. The first front is communication infrastructure. We believe this is an area where the value of lower power dissipation for the same processing power / performance is important. Sometimes it is very important. And we have won the first project for this kind of application. However, there is another target area that is portable equipment, but not necessarily smartphone. There are other, I would say, great opportunities and some of these are really important opportunities that are outside the smartphones and outside the tablets, but they are very important opportunities. And, hopefully, we will have some more good news in the near future.”
Asked if it could be licensing revenues, he replied, “This is something that is possible.”