Changes are afoot on the SOI Consortium website. You’ve seen our great new look. Now we have also brought Advanced Substrate News (known to most as ASN) into our fold.
ASN has been bringing you SOI-related news for over a decade now. Editor-in-Chief Adele Hars will continue leading the charge, working closely with the Consortium’s expanding membership base to bring you key news and fresh perspectives from our industry.
The SOI ecosystem is kicking off a banner year in 2017. For example, we just got the news (read more here) that Consortium member GF is teaming up with Chengdu municipality in China on a new fab offering 22FDX, GF’s 22nm FD-SOI process technology. GF is also expanding Dresden’s capacity by 40 percent and augmenting their Singapore fab’s RF-SOI.
That’s just the tip of the iceberg. Watch these pages for more news from our members and the greater ecosystem (if you’re not yet signed up for our email alerts, please take a moment to fill in the form here). In addition to FD-SOI and RF-SOI, we’ll be further expanding our coverage of other fields leveraging SOI such as MEMS, photonics, power and more.
The Consortium will of course continue offering our extremely successful workshops and training sessions (April in Silicon Valley, June in Tokyo, September in Shanghai plus events in Europe TBA). If you can’t get there yourself, don’t worry. ASN will bring you up-close coverage of these events.
And finally, 2017 marks the 10th anniversary of the founding of the SOI Industry Consortium. We thank you all for your decade of support, and welcome your participation. (If your company is not yet a member, click here to learn more about how to join.)
The SOI ecosystem is more dynamic than ever. Of course we still have plenty of work to do, and we look forward to sharing Consortium and ecosystem successes (and challenges!) with you here at ASN’s new home. We’d love to hear from you – and if you have an idea for a contributed article, please drop Adele an email.
Many thanks. Here’s to the beginning of a dynamic new partnership between the SOI Industry Consortium and ASN.
With best regards,
Carlos Mazure and Giorgio Cesana
SOI Industry Consortium
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
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ASN: In which areas do you see SOI giving designers an edge?
MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.
ASN: What is Leti doing moving forward?
MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….
The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.
ASN: What role does Leti play in the SOI roadmap?
MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.
Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.
ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?
MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.
ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?
MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..
In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.
We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.
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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.
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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?
Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.
Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.
ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?
MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.
ASN: How do you decide what you’re going to work on? Is it your customers?
MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.
On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.
ASN: How much Leti activity is based on SOI?
MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.
All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.
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Here’s a quick “official” summary of Leti:
As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.
Click here to read part 2 of this exclusive interview.
CEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).
On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.
The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.
The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.
If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.
For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which the company says will soon enable manufacturing of 100 Gb/s optical transceivers (read the press release here). This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.
Early in the program (back in 2007), IBM contributed a piece to ASN about why their photonics program is on SOI – you can read that here. (Most all photonics — except the lasers — are on SOI. You can read more ASN photonics pieces from Intel and others here.)
Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.
IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.
IBM presented details at the recent 2015 Conference on Lasers and Electro Optics.
imec’s 28Gb/s silicon photonics platform for optical interconnects and other optical applications will be included in an upcoming multiproject wafer run, reports R. Colin Johnson in EETimes (read the article here). These runs, which are on SOI wafers, are a joint effort by ePIXfab (founded by imec and Leti), Europractice IC and MOSIS. They provide a cost-effective vehicle for fabless researchers in data and telecom.
A new book entitled Silicon-On-Insulator (SOI) Technology, Manufacture and Applications (1st Edition) features contributions by experts at Soitec, GF, TSMC, Leti and more.
Billed as “a complete review of this rapidly growing high-speed, low-power semiconductor technology,” the book covers the entire SOI spectrum, from Moore to More than Moore. It goes into SOI wafer technology, electrical properties, modeling, PD-SOI, FD-SOI, FinFETs and junctionless transistors, RF, ultralow-power, photonics, memory, power and MEMS. (See Table of Contents here.) This book should be a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics, as well as for electrical engineers in the automotive and consumer electronics sectors.
Silicon-On-Insulator (SOI) Technology, Manufacture and Applications is published by Woodhead Publishing, and is also available in print and ebook forms from major online retailers such as Amazon, Elsevier and Barnes & Noble. It was compiled and edited by Oleg Kononchuk, chief scientist at Soitec, France, and Bich-Yen Nguyen, a senior fellow at Soitec, USA.
STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.
While ST signed a licensing agreement with GlobalFoundries a year ago, it was not exclusive, Jean-Marc Chery reminded attendees. Chery is EVP and GM of the Embedded Processing Solutions (EPS) division. The company has racked up 15 active designs in FD-SOI, including multiple design wins in ASICs for networking and consumer markets.
While they weren’t naming names, ST was very bullish about their prospects. They expect FD-SOI to be a significant contributor to the goal of doubling the Digital Convergence Group revenues by Q415. Ramp to volume production begins in Q4 of this year, said Chery, noting with some clear pride that “FD-SOI has moved from a technology opportunity to massive revenue generator in 2015.”
The 15 wins are complex, high-volume, high-ASP products, he said, and there are lots more in the pipeline. They are major wins with major customers, and fall into two main categories: network infrastructure and consumer. He outlined why the two groups are choosing FD-SOI.
For the networking infrastructure customers, there are three major factors of merit:
1. FD-SOI gives them the right performance vs. power trade-off. This is especially true with FD-SOI’s wider flexibility vs. bulk and FinFET because of the greater Vdd range and forward body biasing, which increases energy efficiency and can modulate performance depending on equipment load, he said.
2. Analog performance – for high-speed communications, this is very important, and things like SERDES do much better on FD-SOI than FinFETs.
3. Reliability – especially for memory, where the extremely low error rate makes design of embedded memories and TCAM much simpler and efficient.
For the customers in consumer markets, he cited four things they especially like:
1. As with their confreres in the networking world, they like the performance/power trade-off.
2. But they also really like the low, low leakage in SRAMs, which is key for SOCs, where it’s an important part of the mission profile.
3. There’s huge flexibility in the usage – and when the transistors operate at very low voltages, power consumption is next to nil.
4. FD-SOI is simpler than FinFETs.
Volume production of 28nm FD-SOI will be ramping in Q4 of this year. They will also soon be ready with 14nm prototypes, and he cited the groundwork laid by the alliance in Albany (with IBM, Leti, GF and Samsung).
This slide from the ST FY13 presentation outlines the advantages of FD-SOI for key markets.
(The full ppt is available with the webcast – register here. Courtesy: STMicroelectronics)
Chery sees the volume ramp coming in two waves. After 28nm, the first will be 14nm for set-top boxes. ST, of course, is using FD-SOI in a new generation of chips for advanced set-top boxes based on 64-bit ARM cores (click here for more on that). The second wave will be more ARM-based solutions for complex, high-volume consumer apps.
Writing for Electronics360, Peter Clarke reported that Chery told him, “Crolles can support a selective list of customers that need high complexity and low- or mid- volume. ST will be the preferred manufacturer for those customers.”
Clark also reported that “Of the 15 design wins six are in the communications infrastructure category and 9 are for consumer applications and ST’s STB design is only counted as one of these.” One of the designs is running at 0.6V, he said.
In the course of his presentation, Chery also cited other SOI-based revenue boosters for 2014, including RF-SOI and silicon photonics.
So, we’re looking forward to getting the name of the major foundry that will be both a second-source for ST, and will open up FD-SOI to the industry – watch this space!
Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.
The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.
The complete list of posters and presentations can be seen in the technical program.
This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration. Check the list of participants on those links, and you will see that major players in the field are joining us!
Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.
There will be 2 short courses this year, and 2 fundamentals classes. Those educational tracks are available to you even if you do not register for the full conference.
On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..
Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).
On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.
You could also prefer to take the opportunity to visit the Monterey area.
The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest. The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.
To take full advantage of this outstanding event, register now!
Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.
The latest conference updates are available on the S3S website (http://S3Sconference.org).