Tag Archive Qualcomm

Synopsys-GF-Qualcomm Panel, Leti/Fraunhofer Team Up – FD-SOI Center Stage at Leti Innovation Days

Before summer’s no more than a twinkle in our eyes, let’s take a moment to catch up on a key event where FD-SOI took center stage: Leti Innovation Days. French research powerhouse Leti was celebrating 50 years of innovation, so it was a real gala event.

FD-SOI and other SOI technologies were seen and heard throughout the presentations and in the exhibition spaces. But there were a couple of things that were especially interesting that I’ll cover here in ASN. In particular, a panel discussion with GF, Synopsys and Qualcomm; and the big announcement from Leti and Fraunhofer supporting continued FD-SOI development.

(There were also some great info about body biasing in FD-SOI, but we’ll save that for a future post.)

The Panel & More

A session on Micro-nano Pathfinding and the Digital Revolution featured a fascinating panel discussion on Future Applications and New Technologies. As Rajesh Pankaj from Qualcomm, Alain Mutricy from GF and Antun Domic from Synopsys discussed the prospects, FD-SOI quickly took center stage.

FD-SOI took center stage at this Leti Innovation Days 2017 Panel Discussion. Left to right: Antun Domic, CTO, Synopsys; Alain Mutricy, GF’s SVP, Product Management Group; Rajesh Pankaj, Qualcomm’s SVP Corporate R&D.

Here are some FD-SOI observations from GF’s Alain Mutricy:

  • It’s planar, so it’s not hard to design in.

  • It’s the only technology that can get down to 0.4V, and it has the lowest leakage/cell. That will be key for all mainstream applications (except high-end servers) for at least a decade or two.

  • 12 FDX with forward body bias (FBB) will get 7nm FinFET performance.

  • They’re looking forward to broad FD-SOI adoption. It will enable the next wave of technology and mobile devices.

Synopsys’ Antun Domic noted that:

  • Currently, 50% of silicon area comes from just 3 or 4% of designs. FD-SOI makes design simpler, so the EDA companies are looking for it to open the door to more designs.

  • From a design perspective, three thresholds was standard, but that’s not enough. Place and route could stretch to 10 or 15 corners. FD-SOI simplifies tool flow and cuts mask costs. It’s less complicated than you think.

That tech session, btw, began with an excellent testimonial by Leti partner, Soitec. (Remember: the technological innovation that enabled modern SOI wafers came out of Leti and was industrialized by Soitec.) Check out the snapshot below to get an idea of all the areas that SOI-based technologies address.

Soitec SVP Christophe Maleville shows the many product lines of SOI substrates.

Leti, Fraunhofer & FD-SOI

The big piece of news to come out of Leti Days is that Leti is teaming up with Fraunhofer to “…strengthen microelectronics innovation in France and Germany” (read the press release here). The agreement was signed by Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner at an official ceremony. A lively the press conference followed. Prof. Lakner emphasized that they are working on a common European roadmap, with a clear plan for collaboration on FD-SOI. Europe, he said, is a good idea, and working together, France and Germany can do a lot for industry. For FD-SOI, Leti is focused on the front-end, and Fraunhofer is working on the back-end.

Working together, they can elevate pillars like FD-SOI from the country level to the European level, noted Dr. Semeria. And that puts them in a more elevated position for EC funding initiatives such as an upcoming IPCEI – which stands for Important Project of Common European Interest.

Leti CEO Marie Semeria and Fraunhofer Group for Microelectronics Chairman Hubert Lakner announced “new collaboration to develop innovative, next-generation microelectronics technologies to spur innovation in their countries and strengthen European strategic and economic sovereignty.” (photo credit: Pierre Jayet)

Initially, however, the focus will be on extending CMOS and More-than-Moore technologies to enable next-generation components for applications in IoT, augmented reality, automotive, health, aeronautics and other sectors, as well as systems to support French and German industries. A second phase extending to other partners and countries is possible. We’ll keep you posted.

In closing, I’m sure you’ll all join me in extending hearty congratulations to Leti on their 50th anniversary. And here’s to their next 50 years of innovation – can you imagine what that might bring? It rather boggles the mind, doesn’t it?

 

NXP, Qualcomm, Skyworks to Keynote IoT Theme in Upcoming IEEE SOI-3D-SubVt (S3S) Conference (San Francisco, Oct.’16) – Late News Submissions Open, Advance Program Available

IEEE S3S Conference

10-13 October 2016

Hyatt Regency San Francisco Airport

IEEE SOI3DSubthreshold Microelectronics Technology Unified Conference

Theme: Energy Efficient Technology for the Internet of Things

Late News submissions open and Advance Program available

S3SconflogoThe IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.

This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.

We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.

Our Keynote speakers are decision-makers from major industries:

  • Nick Yu, VP, Qualcomm, will explain why “The Homogeneous architecture is a dead fairy tale”
  • Ron Martino, VP, NXP, will present “Advanced Innovation and Requirements for future Smart, Secure and Connected Applications”
  • Peter Gammel, CTO, Skyworks, will describe “RF front end requirements and roadmaps for the IoT”

Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.

Applications will be illustrated in our session dedicated to SOI circuit implementations.

ieee_logo_mb_taglineYou can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.EDS-Logo-Reflex-Blue-e1435737971222

And you still have time to actively participate by submitting a late news paper before August 31st.

The conference has a long tradition of allying technical and social activities.

This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.

Hyatt Regency San Francisco Airport

Hyatt Regency San Francisco Airport

With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.

Deadline for Late News submissions is

August 31st, 2016

register-now-button

For further information, please visit our website at s3sconference.org or contact the conference manager:

Joyce Lloyd • 6930 De Celis Pl., #36

Van Nuys, CA 91406

T 818.795.3768 • F 818.855.8392 • E manager@s3sconference.org

Reminder re: top SOI Conference – IEEE S3S ’16 (SOI/3D/SubVt) CFP deadline April 15th. Keynotes: NXP, Skyworks, Qualcomm

S3SconflogoDon’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.

As of this writing, the following keynote speakers have been confirmed:

  • Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
  • Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
  • Nick Yu, Qualcomm : topic TBAieee_logo_mb_tagline

Invited speakers include:

  • Jamie Schaffer, GlobalFoundries : topic TBA
  • Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
  • Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
  • Xavier Garros, CEA-Leti : “Reliability of FDSOI”

As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.

Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :

  • SOI
  • 3D Integration
  • Subthreshold MicroelectronicsEDS-Logo-Reflex-Blue-e1435737971222

For current information on the conference visit the S3S website at: http://s3sconference.org/

LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.

IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

Bacchus Entry

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) will be held in Sonoma Valley, CA 5-8 October 2015. (Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.

Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.

EDS Logo PMS3015_revu_smallThe conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

sponsor-ieeeWhile paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.

Program:

Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.

Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.

There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.

Welcome to Doubletree Hotel Sonoma Wine Country

(Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about Ultra-Low Power.

During the Rump session we will debate about the What does IoT mean for semiconductor technology?

Scope of the conference:

The Committee will review papers submitted by May 18 in the three following focus areas of the conference:

 

Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.

 

Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.

 

3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.

Important dates:

Paper submission deadline: 18 May, 2015

Notification of acceptance: 07 June, 2015

Short course date: 5 October, 2015

Conference date: 5 – 8 October, 2015

More details are available on the S3S website.

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.

We learned all this and much more during the very successful 2014 IEEE S3S Conference.

The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.

 S3S14banner

 

Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.

(Photo credit: Justin Lloyd)

S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)

 The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.

 The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.

 

Sub-Threshold Microelectronics

The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.

3D Integration

The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).

Key Fully-Depleted SOI Technical results

Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.

STMicroelectronics and CEA-Leti gave us a wealth of information on:

  • From "Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology" in the S3S '14 "Energy Efficiency" short course by P. Flatresse (Source: STMicroelectronics)

    From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)

    How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).

  •  How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).

The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).

In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.

More than An Order of Magnitude Energy Improvement of

From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)

The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.

On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

FinFET_SOI_IBM_S3S14_Mobility_1

Join the conference in 2015!

Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.

The organizing committee is looking forward to seeing you there!

~~~

 

Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory.  He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT.  Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices.  Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.

Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors.  He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999.  As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials.  As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes.  He has authored or co-authored over 50 papers and holds over 10 patents.

 

 

*RO = ring oscillator

 

 

FD-SOI Front and Center at Very Successful Semicon Europa

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).

This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported.  Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.

 Low Power Conference

It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go.  He indicates a major announcement is impending.

 

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk  — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality.  He sees it having a very long life, with monolithic 3D stacking replacing scaling.

The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.

Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers.  His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Shiro Kamohara, Chief Engineer of the Low Power  Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT.  They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share.  For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.

A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said.  He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.

Power (high & smart), power (very low), 3D and more

During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”.  While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%.  Look for more breakthroughs in their paper at IEDM this December, she said.

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)

ST’s FD-SOI demo (Semicon Europa 2014)

ST’s FD-SOI demo (Semicon Europa 2014)

So it was a great show – kudos to the folks at Semi.  Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.

 

Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

(Image courtesy: SEMI)

 

For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.

And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.

So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.

Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.

For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.

In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.

 

FD-SOI at the Semicon Europa Low Power Conference

The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conferencewhich features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.

Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.

Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.

Other talks include imec on FinFETs, Imagination Technology on MIPS, Qualcomm on the “Landscape for More Moore”, and Leti on FD-SOI and 3D stacking for multicore embedded systems.

Renesas will detail their flavor of FD-SOI, which they’ve been working on for a long time (especially with innovations from Hitachi). They call it Silicon-on-Thin-Buried Oxide, aka SOTB.

David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)

Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.

Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)

The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).

ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.

 

Power and 3DI

A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.

Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.

Hope to see you in Grenoble!

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

S3Sheader

(For best rates, register by September 18th.)

The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.

Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.

This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.

 

Short courses: Monolithic 3D & Power-Efficient Chip Tech

On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.

The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.

The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.

 

Conference program

The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.

Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.

Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.

We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.

Our technical content is detailed on our program webpage.

 

Panel discussions, cookout & more

Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.

SFstreetsignOur conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.

The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.

Please take a moment to learn more about our conference by browsing our website or downloading our advance program.

To take full advantage of this outstanding event, register before September 18!

Special hotel rates are also available from the dedicated hotel registration page.

The committee and I look forward to seeing you in San Fransisco.

– Bruce Doris, S3S General Chair

 Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

SST article details Leti’s Monolithic 3D presentation at Semicon West ’14

An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for scaling’.” Cronquest puts the big picture in perspective, while providing plenty of technical information. He ends by reminding readers that this and other key work will be further detailed at the IEEE S3S Conference (S3S = SOI + 3D + Subthreshold Microelectronics) October 6-9, 2014 at the Westin San Francisco Airport (see the conference website here).

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four papers in the Highlights Sessions covered SOI devices for the 10 and 14nm nodes.

There were so many great SOI-based papers that we’re going to cover this conference in two posts.  This post covers the three big 14nm FD-SOI and 10nm FinFET papers. Summaries and abstracts of all the others will be covered in Part 2 (click here to read Part 2).  Please note that as of this posting date, the papers are not yet available from the IEEE Xplore site – but they should be shortly.

Read on!

Top SOI Highlights from the Symposium on VLSI Technology

2.3: 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications. O. Weber et al. (STMicroelectronics, CEA-LETI, IBM)

This is the big paper we’ve been waiting for – the one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs. We still don’t have a side-by-side FD-SOI v. bulk FinFET comparison, as there is scant data at comparable leakage on bulk FinFETs at 14nm publicly available with which to compare. But based on what they’ve been seeing and some extrapolation, the FD-SOI  technology developers see the figures presented in this paper as a big win.  We’ve already seen hints of this in a recent ASN piece (click here to see that one) showing 14nm FD-SOI matching 14nm bulk for performance and coming in at a much lower cost.  Now in terms of performance, here’s the VLSI paper detailing the FD-SOI side of the story.

The authors confirm a scaling path for FD-SOI technology down to 14nm, using strain-engineered FD-SOI transistors. Compared to 28-nm FDSOI, this work provides an 0.55x area reduction from scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back-bias, an additional 40% dynamic power reduction for ring oscillators is experimentally demonstrated. Moreover, a full single-port SRAM is described, including a 0.081 μm2 high-density bitcell and two 0.090 μm2 bitcell designs used to address high-performance and low-leakage/low Vmin requirements.

Paper-T2.3-14nm-FDSOI-Technology-for-High-Speed-and-Energy-Efficient-Applications

(Courtesy: VLSI Symposia)

 

TEM of an FD-SOI nMOS transistor, showing gate-to-drain capacitance components and experimental values. From 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications (O. Weber et al., STMicroelectronics, CEA-LETI & IBM)

 

 

 

 

 

2.2: A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI.  K.-I. Seo et al.  (Samsung, IBM, ST, GF, UMC)

This paper covers the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing. Targeting low-power and high-performance, it offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 μm2 SRAM bit-cell – and this part was on SOI –  was reported with a low corresponding static noise margin of 140 mV at 0.75 V.  The team developed intensive multi-patterning technology and various self-aligned processes with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce.

Paper-T2.2-A-10nm-Platform-Technology-for-Low-Power-and-High-Performance-Applications-Featuring-FINFET-Devices-with-Multi-Workfunction-Gate-Stack-on-Bulk-and-SOI

(Courtesy: VLSI Symposia)

 

Projected scaling trend, featuring the tightest contacted poly pitch (CPP=64 nm) and metallization pitch (Mx=48 nm) ever reported, on both bulk and SOI substrates. From A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, by K.-I. Seo et al.  (Samsung, IBM, ST GF, UMC)

 

 

 

 

2.4: Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

The authors demonstrated high performance (HP) s-SiGe pMOS pMOSsfinFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. They also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and L G~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe FinFETs are strong candidates for future HP and low-power applications.

VLSI_2.4

(Courtesy: VLSI Symposia)

 

TEM images of the most aggressively scaled SiGe FinFET reported to date with a fin width of ~8nm and gate length of ~15nm. From Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

 

 

 

Rump Sessions

There were also two rump sessions held during the conference, which were co-chaired by Soitec CTO Carlos Mazure. The SOI ecosystem was well-represented, the rooms were packed and the debate lively.

Rump Session 1: Who gives up on scaling first: device and process technology engineers, circuit designers, or company executives?  Which scaling ends first – memory, or logic? Panelists: M. Bohr, Intel; M. Cao, TSMC; J. Chen, Nvidia; S-H Lee, Hynix; T-J King Liu, UC Berkeley; K. Nii, Renesas: R. Shrivastava, Sandisk; H. Jaouen, STMicroelectronics; E. Terzioglu, Qualcomm

The take-away here is that the majority of panelists and attendees see company executives giving up on scaling in the face of rising costs.

Rump Session 2: 450 mm, EUV, III-V, 3D; All in 7nm? Are you serious?!  Panelists:  W. Arnold, ASML;
 R. Gottscho, Lam Research; K. Hasserjian, AMAT; S. Iyer, IBM;
 C. Maleville, Soitec; A. Steegen, IMEC

The general consensus was that 3D integration is needed and will be adopted at the 7nm node due to delays and the high cost of the EUV and III-V, and the lack of 450mm wafer supply and support.