Tag Archive Renesas

ByAdele Hars

SOI Wafers on the Move – News from Soitec with Samsung, Simgui, China Mobile, Renesas & More

The world’s SOI wafer leader, Soitec is posting strong sales and issuing a steady stream of compelling announcements. This is clearly good news for everyone in the SOI ecosystem, as the outlook for the various families of SOI wafers is excellent.

Soitec CEO Paul Boudre told ASN, “I’m excited because of the fundamentals behind the growth. Reaching down the supply chain gives us the ability to help our customers with the next generation. We’re not in a technology push, but in a technology pull. It’s long-term growth we’re seeing.”

Paul Boudre, CEO, Soitec

Soitec has brought people from the device side into the company to better understand the solutions customers need, he said. They’re talking to the carmakers, telcos and more, working one-on-one with them to understand the constraints and the problems they are trying to fix, in order to deliver a solution based on the Soitec product roadmap.  Boudre is particularly excited about 5G. It’s not just new handsets and systems: the entire infrastructure will require a massive upgrade, across which Soitec has a role to play supplying SOI wafers.

They also have other SOI and engineered substrates for specific markets like filters, displays, imaging and power. He adds that they’re seeing nice growth in SOI wafers for photonics, driven by cloud computing, and for smart power in markets like automotive and white goods.

Here’s a roundup of some recent developments. Chips made on RF-SOI wafers are in every mobile phone made on the planet these days, so lets look at what they’re doing there first. We’ll follow that with an update on the surge of activity on FD-SOI wafers.

Simgui, RF & Power

It’s no secret that the runaway success of RF-SOI for front-end modules (FEMs) in mobile phones has stretched wafer capacity mightily. To help address this, in February 2019 Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. The two companies redefined their manufacturing and licensing relationship to better serve to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics.

(Image courtesy: Simgui)

Since the two companies signed their original licensing and technology transfer agreement in May 2014, Simgui has mastered Soitec’s Smart Cut™ proprietary process to deliver world-class RF-SOI and Power-SOI products. Simgui’s strategic partnership with Soitec allows them to use the same tools and processes to deliver the same products meeting the same specifications.

Simgui has invested in their Shanghai fabrication line in order to double annual 200mm SOI wafer production capacity from 180,000 to 360,000. The fab is production ready, having been qualified by multiple key customers inside and outside China.

Simgui CEO Dr. Jeffrey Wang notes, “China has design, wafer manufacturing and good momentum in the IC industry. We are committed to our strategic partnership with Soitec to keep advancing SOI as China’s key differentiator.”

With China Mobile

China Mobile’s interest in the SOI ecoystem is clear: they’ve presented at the SOI symposia in Shanghai for two years running now. In a February 2019 press release, Soitec announced that they’ve joined the China Mobile 5G Innovation Center – and they’re the first materials supplier to do so. The China Mobile 5G Innovation Center is an international alliance chartered to develop 5G communication solutions for China, the world’s largest wireless communications market with 925M mobile subscribers. The Center aims to accelerate the development of 5G by establishing a cross-industry ecosystem, setting up open labs to create new products and applications, and fostering new business and market opportunities.

Soitec’s RF-SOI wafers have been critical in the deployment of 4G communications, and the opportunity in 5G is even bigger. Plus the company’s FD-SOI wafers enable the technology that brings unique RF performance, making it an ideal solution for many applications including mmWave communications such as 5G transceivers. They are also enabling full RF and ultra-low-power computing integration for IoT and edge computing.

For Samsung Foundry

In January 2019, Soitec announced that they have expanded their collaboration with Samsung Foundry on the FD-SOI wafer supply, securing the high-volume Samsung needs to meet industry’s current and future demands in consumer, IoT and automotive applications. The agreement is built on the existing close relationship between the companies and guarantees wafer supply for Samsung’s FD-SOI platform starting with the 28FDS process.

“Samsung has been committed to delivering transformative industry leading technologies,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “FD-SOI is currently setting a new standard in many high-growth applications including IoT with ultra-low-power devices, automotive systems such as vision processors for ADAS and infotainment, and mobile connectivity from 5G smartphones to wearable electronics. Through this agreement with Soitec, our long-term strategic partner, we hope to lay the foundation for steady supply to meet high-volume demands of current and future customers.”

“This strategic agreement validates today’s high-volume manufacturing adoption of FD-SOI,” said Christophe Maleville, Soitec’s Executive Vice President, Digital Electronics Business Unit. “Soitec is ready to support Samsung’s current and long-term growth for ultra-low power, performance-on-demand FD-SOI solutions.”

Silicon Catalyst Partner

In February 2019 Soitec announced they’d become a strategic partner in Silicon Catalyst’s start-up incubator. Silicon Catalyst is a Silicon Valley-based incubator providing silicon-focused start-ups access to a world-class network of advisors, design tools, silicon devices, networking, access to funding and marketing acumen needed to successfully launch their businesses.

(Image courtesy: Soitec, Silicon Catalyst)

Soitec will engage in this start-up ecosystem to gain insight into the newest technologies and applications across high-growth markets, and to guide nascent technologies to successful market penetration.

“As a Strategic Partner of Silicon Catalyst, Soitec has a unique opportunity to grow our visibility among early-stage semiconductor companies,” said Thomas Piliszczuk, Executive VP of Global Strategy for Soitec. “Engineered substrates give semiconductor related start-ups a competitive edge in developing new high-performance, energy-efficient solutions.”

Pete Rodriguez, CEO of Silicon Catalyst said, “Soitec is creating technical advances that are enabling the next generation of products across many market segments. Their SOI technology is a key ingredient to meet the diverse challenges for breakthrough differentiated semiconductor products, combining ultra-low power with excellent analog/mixed-signal performance.”

Energy Harvesting with Renesas

And finally, jumping back a few months, at the end of 2018 Soitec announced that their SOI wafers are at the heart of a new Renesas SOTBTM energy harvesting chipset, opening a self-powered future for IoT devices. SOTB is how Renesas refers to its FD-SOI technology.

(Image courtesy: Renesas)

(BTW, here at ASN we’ve been covering the work that Renesas has quietly done on this technology since 2005 (!).  And we did a piece  about an EETimes Japan article back in 2015 that revealed the launching of the 65nm work. )

Soitec supports the Renesas SOTB chipset with a special version of its FD-SOI wafer product line. The new Renesas SOTB-based chipset overcomes the energy constraints of IoT devices and reduces the power consumption to approximately one-tenth that of the existing products in the market today. That makes the chipset perfectly suited for extreme low-power, maintenance-free and energy harvesting applications including wearable devices, smart home applications, smart watches, portable appliances, infrastructure monitoring systems, industrial, business, agricultural, healthcare, as well as health and fitness apparel, shoes, drones and more.

Renesas has developed its energy harvesting chip using its unique SOTB 65nm process technology that achieves both low active current of 20 μA/MHz and deep standby current of 150 nA. As a result, Renesas’ SOTB chipsets offer enhanced control of the transistor electrostatics and reductions in both the standby and active currents to levels never before achieved. Additionally, Renesas has successfully delivered the dopant-less channel to suppress Vth variability for the ultra-low voltage operation, and the ultra-low power back bias control to reduce the standby current at the same time.

“To spur innovations in IoT and consumer applications, we have integrated our exclusive energy-harvesting SOTB technologies into our Energy Harvest Controller,” said Mr. Toru Moriya, Vice President of Renesas’ Home Business Division, Industrial Solutions Business Unit. “We are confident that our SOTB technology built on Soitec’s ultrathin substrates can deliver unmatched capabilities for developing maintenance-free IoT devices that never require power supply or replacement, giving rise to a new IoT global market based on endpoint intelligence.”

(click to enlarge) Block diagram of the Renesas R7F0E Embedded Controller, their first device based on their SOTB (aka FD-SOI) technology. Target applications are battery-free connected IoT sensing devices with endpoint intelligence. (Image courtesy Renesas)

The new R7F0E Embedded Controller is the first device based on Renesas’ SOTB technology. Developers can now design applications that need no battery or recharging.  The R7F0E features: an Arm® Cortex® -M0+;  operating frequency up to 32 MHz, and up to 64 MHz in boost mode (that’s body bias in action!); memory of up to 1.5 MB flash, 256 KB SRAM; and active current consumption while operating at 3.0V of just 20 µA/MHz, and in deep standby of 150 nA with real-time clock source and reset manager. As of this writing, Renesas indicates it’s engaging select customers through July 2019, with mass production in 4Q19. Read more about the R7F0E on the Renesas website.

ByAdele Hars

Share This! Terrific Guide to All Things FD-SOI in GSA Newsletter

Manuel Sellier, Product Marketing Manager at Soitec

Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It’s in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance).

If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you’ll want to share this piece with them right away.

Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What’s more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don’t worry that this might be too technical: Sellier’s writing is thoroughly accessible (and engaging!) for anyone in the industry.

He starts with the wafer history, then quickly moves on to the features from the designer’s standpoint. And he puts it all in a business perspective. I can’t recommend this piece enough – even if you think you know everything already yourself, you’re sure to learn something new.


Great FD-SOI start for 2016: Samsung, GF, Renesas, NXP/Freescale, ST, Soitec

Just a month into 2016 and we already have a raft of FD-SOI news from Samsung, GlobalFoundries, NXP/Freescale, Renesas and more. And of course RF-SOI continues ever stronger.

logo_soiconsortiumHere’s a quick update of what we’ve been seeing, starting with news from the recent SOI Consortium forum in Tokyo. Many of the presentations are now available on the SOI Consortium website – but keep checking back for more.


Samsung: 28nm FD-SOI hits maturity, mass production starts 1Q2016

Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung, gave a talk entitled, The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits.

Here are his key messages with respect to 28nm FD-SOI:

  • The technology, which was qualified in 2015, is now ready for mass production, with the first commercial production set for 1Q2016.
  • Yield levels are excellent.
  • There were 12 tape-outs in 2015 in connectivity, security, games, set-top boxes, application processors for consumer and automotive, plus CMOS image sensors (aka CIS — for an excellent explanation of why FD-SOI is right for CIS and why leaders in this arena are considering it, see Junko Yoshida’s recent EETimes piece here).
  • The 16 tape-outs planned so far for 2016 expand to a wider range of automotive apps, plus we see the first in IoT and wearables, MCUs and programmable devices.
  • A production PDK for a version of 28nm FD-SOI with RF integration will be available in 2Q16.
  • eNVM (embedded non-volatile memory) will be ready in 2018.

For other key Samsung slides showing data on their success in manufacturability, check out EETimes.


GlobalFoundries: RF-SOI for 5G, FD-SOI Customers Engaged

Subramani Kengeri, VP of Global Design Solutions at GlobalFoundries talked about their 22nm FD-SOI, in his presentation Enabling SoC Innovations with 22FDXTM. He indicated that they’ve got over 40 customers engaged on it. Key points they’re hitting on that make them bullish on their prospects include:

  • FinFET-like performance and energy efficiency at 28nm cost
  • Ultra-low power consumption with 0.4V operation
  • Maximum flexibility in power/performance trade-off with software-controlled body biasing
  • Integrated RF cuts RF power in half and means designers don’t need an extra RF chip.
  • They’ll reach high-volume production by the middle of 2017.

For more on how GF see 22FDX as very well-positioned for IoT, see their Foundry Files blog. There’s also a really good piece in EEJournal by Byron Moyer entitled, A Non-FinFET Path to 10 nm – GlobalFoundries’ FD-SOI Alternative.

GF is of course also a dominant RF-SOI player, as seen in RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries. The presentation, which is available on the SOI Consortium website, notes that, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results,” so that, “SOI holds great promise in delivering on the key requirements of 5G systems.” (For an overview of GF’s RF-SOI position, see RF-SOI is IoT’s Future, and the Future in Bright on their Foundry Files blog.)


Renesas: in FD-SOI production at 65nm this year

Shiro Kamohara, Chief Engineer, Renesas Electronics Corp., lead off the presentations with Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era.

A Nikkei article reported from the conference that Renesas will be in mass production of 65nm FD-SOI – which they call Silicon-on-Thin-Box, or SOTB – for IoT products this year. Renesas reports the move cuts power to a tenth of what they’d seen in bulk. You can see the original article in Japanese here or a translated version here.


Soitec: wafers ready for mass adoption

Soitec_SOIsourcingIn the presentation Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms, Soitec Sr. VP of Digital Electronics Group Christophe Maleville, Senior Vice President, Digital Electronics BU provided data on every conceivable aspect of SOI wafers for FD-SOI and RF-SOI. He explained adaptations in the company’s Smart CutTM manufacturing technology that achieve astonishing levels of uniformity and thickness – or rather, thinness! With new metrology, they can predict and protect against variability in devices. And they are now producing FD-SOI wafers for 28nm processes with uniformity of +/- 1 atomic layer.


ST: making the case

For analog/RF, RF/mmW and mixed-signal/high-speed designers, Andreia Cathelin, Senior Member of Technical Staff at STMicroelectronics explained how and why FD-SOI makes their lives easier. Her presentation, FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs drills down to the technical for these folks.

Pietro Maestri, ST’s RF Product Line Director presented ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration. (BTW, we had an excellent high-level article by ST when H9SOI_FEM was first announced, describing the challenges faced by designers of smartphone front-end modules (FEMs) and how their H9SOI_FEM solves them – read it here.)

For anyone wondering about the status of FD-SOI following the just-announced company reorganization, COO Jean-Marc Chery told EETimes’ Peter Clarke that they remain fully committed to the technology. As noted in the article (read the whole thing here), “Chery emphasized that, following the announcement of ST’s withdrawal from STB and home gateway markets and of a proposed redeployment of 600 engineers, the company is now focused on automotive and Internet of Things applications and that therefore FDSOI is a core manufacturing process. Indeed it could be argued that moving engineers familiar with FDSOI from the STB group into MCUs and automotive will help to proliferate the technology through the company.”


NXP/Freescale: Loving FD-SOI

In another recent EETimes article, Peter Clark reported from the NXP “Smarter World Tour” that the newly merged NXP-Freescale is very bullish on FD-SOI (see the full article here).

He cites Goeff Lees, the GM for the MCU part of the merged businesses, who especially likes 28nm FD-SOI for IoT and MCUs. Ticking off the reasons, he lists energy efficiency, cost, analog support, security, temperature control and lower leakage current. In fact, he says, “I believe all MCU vendors could move to FD-SOI.” Wow.

So stay tuned – here at ASN we’ve got contributions from NXP/Freescale, Synopsys, GlobalFoundries, Surecore and more at the top of the 2016 queue. Yes, it’s going to be a good year.

ByGianni PRATA

Renesas Coming Out with 65nm FD-SOI chips (but they call it SOTB), says EETimes Japan

Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.

If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.

Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?


FD-SOI Front and Center at Very Successful Semicon Europa

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

An ST key ring sporting their new FD-SOI logo (Semicon Europa 2014)

Yes, GlobalFoundries is hot on FD-SOI. Yes, Qualcomm’s interested in it for IoT. Yes, ST’s got more amazing low-power FD-SOI results. These are just some of the highlights that came out of the Low Power Conference during Semicon Europa in Grenoble, France (7-9 October 2014).

This was Semicon Europa’s first time in Grenoble, the heart of FD-SOI country, and it was a terrific success. There was a ton of energy, a raft of very well-attended conferences, and vendors on the show floor were clearly pumped up by the high-quality lead generation they reported.  Attendance (over 6K visitors) and floor space were both up (>40%). Highlights follow.

 Low Power Conference

It was standing-room only for ST COO Jean-Marc Chery’s keynote. In addition to apps in FD-SOI for mobile, consumer and network infrastructure, he was very bullish on automotive, noting that this is a place FinFETs can’t go.  He indicates a major announcement is impending.


ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

ST slide on an automotive app on FD-SOI (Semicon Europa 2014 Low Power Conference)

Next up, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they were seeing interest, he said yes. Asked if they have customers lined up, he said yes. So watch this space – there’ll be news soon!

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

GlobalFoundries slide on the FD-SOI value proposition (Semicon Europa 2014 Low Power Conference)

ST Fellow and FD-SOI guru Thomas Skotnicki gave an excellent talk  — he’s been ST’s champion of the concept for 26 years, and noted that the breakthrough by Soitec a few years ago in making the ultrathin SOI wafers with ultrathin box made industrialization a reality.  He sees it having a very long life, with monolithic 3D stacking replacing scaling.

The Qualcomm Technologies talk by Senior Program Manager Mustafa Badaroglu was largely about FinFET challenges, and while he observing that SOI was the best solution for leakage, cost concerns remain. With respect to FD-SOI, however, he did note that 28nm is very attractive for IoT apps. Interesting, too, that he stayed for all the other presentations and asked a lot of incisive questions about FD-SOI.

Fabien Clermidy, Sr. Expert at Leti, looked at low-power multiprocessing for markets spanning embedded through servers.  His team’s working at full bore on the Euroserver project, which leverages FD-SOI, ARM cores, monolithic 3D – you name it. He also gave some impressive details on the FRISBEE DSP, which operates from 0.3V to 1.2V, getting performance of 200MHz at the low end of the power supply and 2.7 GHz at the high end.

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Leti slide on the Euroserver (Semicon Europa 2014 Low Power Conference)

Shiro Kamohara, Chief Engineer of the Low Power  Electronics Association & Project (aka LEAP) and Renesas gave a compelling talk about their vision of FD-SOI, which they call SOTB (for silicon-on-thin-box) for IoT.  They see lots of possibilities, including for getting more life out of older nodes and fabs. They have even demonstrated a 32 bit CPU on 65nm SOTB with back bias that operates eternally (that’s right!) with ambient indoor light – clearly something to watch for.

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

LEAP slide on SOTB (aka FD-SOI) for IoT (Semicon Europa 2014 Low Power Conference)

A talk by Soitec CTO, Carlos Mazure focused on the SOI wafers for current and future generations of FD-SOI and FinFETs, as well as for RF. He noted that RF-SOI wafers for switches and antenna tuners enjoy a >80% market share.  For 28nm, he cited VeriSilicon’s figures from the recent Shanghai FD-SOI forum that indicated FD-SOI savings of 19% in area, 71% in standby power and 58% in power over bulk.

A fascinating talk by Handel Jones of IBS (see his ASN articles here) looked at IoT. We need to be thinking about billions of chips – not millions – at under $10, he said.  He sees the industry at a tipping point now, with more local intelligence coming. IBS is convinced that FD-SOI is the best technology for IoT apps, in large part because of memory driving cost, size and power consumption requirements.

Power (high & smart), power (very low), 3D and more

During the Semicon Europa Power Electronics conference, Soitec BizDev Manager Arnaud Rigny looked at high voltage devices on SOI, in “smart substrates for smart power”.  While these wafer substrates can be either “thick” or “thin” SOI (referring to the top layer of silicon), smart power (which includes analog, logic & power) typically uses a relatively thin SOI. However, in this case the top silicon uniformity needs to be greater. He said it’s a good growth area for Soitec, which is seeing an uptick of 20% in thin SOI wafers for smart power. The biggest market there is automotive.

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

Soitec slide on SOI for smart power (Semicon Europa 2014 Power Electronics Conference)

There was a great turnout for Leti’s talk by Senior Scientist Claire Fenouillet-Béranger in the TechArena showing their monolithic 3D integration scheme. They’re reporting savings in area of 55%, performance of 25% and power of 12%.  Look for more breakthroughs in their paper at IEDM this December, she said.

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

Leti’s presentation on monolithic 3D integration (Semicon Europa 2014 Tech Arena)

And finally, out on the show floor, in addition to their great FD-SOI keying (see above), ST had a cool – make that freezing – demo showing the effectiveness of back biasing in FD-SOI at very low power and very, very cold temperatures. Officially titled “Temperature self-compensation on 32b RISC FDSOI28 thru dynamic body biasing down to 0.35V”, we saw the chip could run stably at 20MHz with a supply voltage of just 0.45V – that’s amazing in itself – but that it should maintain stability at -22oC is absolutely phenomenal. Body biasing dynamically compensates for the temperature fluctuations. This points up just how important FD-SOI will be for ultra-low power IoT, and in this case for things like medical apps. (If you’re very patient, you can watch this blogger’s attempt to capture the ST demo on her iPhone here.)

ST’s FD-SOI demo (Semicon Europa 2014)

ST’s FD-SOI demo (Semicon Europa 2014)

So it was a great show – kudos to the folks at Semi.  Next year it will be in Dresden, and alternate between Grenoble and Dresden from then on. And now we know that interesting things are promised for FDSOI in Dresden, we’ll certainly look forward to 2015.



SOI: Looking Back Over a Year of Moving Forward (Part 1, FD-SOI)

2014’s going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise.

But before we look forward (which we’ll do in an upcoming post), let’s consider where we’ve been and some of the highlights of the last year.  In fact, there was so much happening that we’ll review 2013 in two posts – this post is about FD-SOI; in the next post we’ll cover RF-SOI and FinFETs.

Highs, lows, and the promise of an extra day

It was just a year ago that you read in the first ASN post of 2013 about ST-Ericsson’s NovaThor™ L8580 ModAp: at 2.5GHz it was “the world’s fastest and lowest-power integrated LTE smartphone platform” at CES ’13 in Las Vegas.  Then in February in Barcelona ST announced that its 28nm FD-SOI technology clocked in at 3GHz, but what was really amazing was that it got 1GHz using using just 0.6V VDD, aka the “supply voltage”, which is the main voltage “in” that powers the chip. No one had been able to run stably on that low a voltage before.  28nm FD-SOI got you a full extra day before you had to recharge your device.

But then of course came the sad news that the plug was pulled on ST-E. Happily the technology moved into the ST fold, and the 28nm process is now ramping in volume, with 14nm is set to debut shortly.


ST300mmFDSOIwaferMay was a big month. ST’s FD-SOI got the EETimes ACE Award for Energy Technology – and the company announced it had started winning FD-SOI customers. We also got the news of a big public-private funding boost, to the tune of €360M, for the Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe). It is lead by ST, with production lines in Dresden and Grenoble. Among the other companies and institutions involved are GlobalFoundries, Soitec, Mentor, Leti, imec, Ericsson and UCL. A 3-year public-private project involving 500 engineers from 19 members in seven countries, it’s looking to enable volume manufacturing in Europe from 28nm down to 10nm.

Also in May, Leti told us that they’d gotten silicon layers down to 3.5nm, and for boosting pFETs with SiGe, were seeing better results with FD-SOI than bulk FinFETs. What’s more, they found that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!

In August, the French government upped the ante with a 600 million Euro investment in the Nano2017 program, which was in addition to the 3.5 billion Euros that ST and partners had already pledged, bringing the total to 4.1 billion Euros (about $5.4 billion).

In October, Leti said it would have the 10nm FD-SOI PDK ready in June of 2014.

In November, the wafer supply chain got a boost when SOI wafer suppliers Soitec and SunEdison (formerly MEMC) ended their longstanding legal feud and entered into a patent cross-license agreement.

At IEDM in December Leti announced UTSOI2, a compact model for electrical simulations. Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers use before they run silicon. Dedicated to Ultra-Thin Body and Box (UTBB) FD-SOI technology, UTSOI2 accurately describes independent double gate operation for sub-20nm nodes. Also at IEDM, ST, Leti, IBM, Renesas, Soitec and GlobalFoundries presented the big paper showing great results for 14nm FD-SOI.

So 2014 promises to be an excellent year.  Stayed tuned – next up we’ll review the great strides made in RF-SOI and SOI-FinFETs.

From all of us here at ASN, wishing you a safe, happy, healthy, prosperous and innovative New Year!


The FD-SOI Papers at IEDM ’13

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.

Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.

9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries) 

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012


Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 


and below.

The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”


7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.


20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.


12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.


33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.


2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.


5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (Tw) than predicted by the T6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

ByGianni PRATA

FinFET vs. FD-SOI at IEDM (EETimes)

EETimes predicts a FD-SOI vs. FinFET showdown at the upcoming IEDM conference. At Session 9
on advanced CMOS platforms TSMC will provide details on the company’s 16nm bulk FinFET
CMOS process, followed by a paper on the 14nm FD-SOI process by STMicroelectronics, Soitec,
Leti, IBM, GlobalFoundries, and Renesas.


ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group.

Introduction to FD-SOIAs you no doubt know by now, at CES a few weeks ago, ST-Ericsson showed the new NovaThor L8580, which integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die. Process technology and manufacturing credit goes to ST.  In a live video from the show, the chip reached 2.8GHz in a high-performance demo, and in a low-power demo hit 1GHz using just 0.636V (which would take 1.1V on bulk).

Since then, Giorgio Cesana, Director of Technology Marketing at STMicroelectronics, has been everywhere, responding to questions from readers and correcting misunderstandings as they arise.

One of the top things people want to know more about is biasing in FD-SOI, which can provide a big performance boost or huge power savings.

LinkedIn In case you missed it, here’s what Giorgio had to say to questions posed in the big LinkedIn Semiconductor Professional’s Group:

Thank you all for this interesting discussion and for giving me the opportunity to provide more details about the ST 28nm FD-SOI technology. I hope this clarifies any misunderstandings.” 

Body bias, or more properly back bias (because biasing is done on the back face of the transistor) is a way to electrically control the Vt of the device by controlling of the polarization of the wells. 

Conceptually, it is like having the planar transistor controlled by two gates: the real “classical” gate, we build with a HKMG, gate-first manufacturing approach, and a virtual gate (represented in the video with a transparent gate below the transistor) that represents the capability to control the transistor through biasing. 

The back gate is the “virtual” one. It does not require any extra manufacturing steps to be fabricated. It is created simply by polarizing the well. 

The particular FD-SOI technology that ST is using, called UTTB (Ultra Thin Body and Box), benefits from a extremely thin (25nm) Buried Oxide (BOX) which enables extremely efficient control of the transistor threshold voltage through the biasing, up to 80mV/V. In addition, because of the insulator in FD-SOI, biasing is not limited to 300mV like in bulk technologies, allowing an extremely wide dynamic control of the transistor Vt. 

In terms of biasing efficiency, this past Dec 10th we published some figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at 0.6V. 

That said, exploiting body biasing is a matter of making a design that provides an independent supply to the wells, managed through the power supply controller, to optimize the Vt to reach proper energy efficiency, balancing the static and dynamic part of the power consumption. Of course biasing conditions should be considered at design optimization and sign-off phase. 

Finally body/back biasing in FinFETs simply does not work, because the transistor channel is vertical and the gate controls 3 sides of the channel. The 4th side (the one sitting on the substrate) is too narrow to be influenced through body biasing. Body biasing is simply not an option with FinFETs. 

Someone at one of the big programmable device companies then asked a follow-up question on the implementation. Giorgio responded:

In 28nm FD-SOI, threshold-voltage centering is a function of the gate work function, where the Vt is controlled by implanting a ground plane (GP) below the BOX (Buried Oxide). Depending on its type (N or P), Vt can be raised by more than 50mV, allowing the manufacturer to offer two device flavors: regular Vt and low Vt. 

Threshold voltage is also statically controlled by modulating the gate length. ST’s multi-channel standard-cell library allows us to modulate the gate length up to +16nm, offering a static leakage control of up to 50x for a single Vt design, almost twice the leakage control offered by dual-Vt designs plus multi-channel libraries of competing bulk planar technologies. 

Body bias is just one way to modulate the threshold voltage, and the dynamic nature of the control allows new and innovative design solutions to be implemented for extremely energy efficient designs.

I should note that body-bias usage is not mandatory in FD-SOI: we can make devices without using it and which still benefit from a good speed/power balance, low Vmin memories, better device variability, and all the other benefits FD-SOI processing offer. Chip architects can also decide to limit body-bias adoption only to some critical blocks/IPs in the SoC for the best trade-off between optimal energy efficiency and implementation simplicity. 

For further reference, you may read F. Arnaud, “Switching Energy Efficiency Optimization for Advanced CPU thanks to UTBB Technology,” IEDM 2012.

To reader questions posted in the comments sections of SST and EETimes articles, Giorgio cleared up some other misunderstandings. Here is a summary of some of the things he said:

FD-SOI vs. PD-SOIUltra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect.

In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

Self-heating: Self-heating is also a problem that exists with Partially-Depleted SOI technologies, where the Buried Oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects.

UTBB FD-SOI technology offers two advantages to overcome this self-heating:

– The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;

– The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.

Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

Manufacturability: to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.

Additional recommended reading:

– O. Faynot et al, “Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond”, International Electron Device Meeting Technical Digest, 2010
– Advantages of UTBB FD-SOI:  A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012*, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES.

*Editor’s note: ETSOI is what IBM calls its flavor of FD-SOI.


To keep up-to-date on the latest in SOI-related news, please join us at the Advanced Substrate News LinkedIn group.

ByGianni PRATA

Renesas Technology announced that it has developed a high-density capacitorless “floating body” twin-transistor RAM

Renesas Technology announced that it has developed a high-density capacitorless “floating body” twin-transistor RAM (TTRAM), which it says will allow fast, high density storage to be embedded in power-efficient system-on-a-chip devices built with 65-nm SOI CMOS.