Tag Archive RF SOI

ByGianni PRATA

“…we are ramping a large number of SOI switch designs on our industry-leading SOI process,” noted TowerJazz CEO Russell Ellwanger in the company’s September ’13 newsletter.

“…we are ramping a large number of SOI switch designs on our industry-leading SOI process,”
noted TowerJazz CEO Russell Ellwanger in the company’s September ’13 newsletter. The SOI
switch designed in Netanya “…received impressive traction and is winning business for the RF/HPA
business unit,” adds Ori Galzur, Vice President of TowerJazz’s Worldwide VLSI Design Center. He
also notes that the design team has released STD cell libraries for their SOI platforms.

ByAdministrator

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest

Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size.

The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The new TaRF5 process delivers approximately 25% lower insertion loss (at 2.7 GHz) and approximately 40% size reduction (for SP10T), compared to the comparable devices fabricated with the TaRF3 process.

TOSHIBA_SP10T_INSERTIONLOSS_131007_

Insertion loss on Toshiba SP10T RF antenna switches (Graphic: Business Wire)

Sample shipments of the SP10T (which stands for Single Pole Ten Throw Switch) have now started.

The TarfSOI™ process was first developed in 2009. The SOI advantage, says Toshiba, is the insulating film under the channel of the MOSFET, reducing stray capacity to improve speed and power saving of the CMOS LSI. The latest improvements can lead to longer battery operating time and smaller mounting space, which can also contribute to smaller sizes for products in which they are used, says the company.

Since the first TarfSOI generation, Toshiba has been continually developing new generation processes and devices offering improved performance. The company explains that RF antenna switch requirements for the current LTE and next-gen LTE-Advanced are leaning towards multi-port and complex functions. That’s why, to meet those market demands, Toshiba plans to continue to develop products with low insertion loss and smaller sizes.

SOI for front-end RF solutions is rapidly gaining ground throughout the industry. In recent months, announcements have been made by Peregine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement recently found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth. Who’s next?

 

ByGianni PRATA

MagnaChip and the National Nano Fab Center (“NNFC”) have entered into an SOI RF CMOS technology transfer agreement that combines MagnaChip’s specialty manufacturing expertise with NNFC’s robust RF technology.

MagnaChip and the National Nano Fab Center (“NNFC”) have entered into an SOI RF CMOS technology transfer agreement that combines MagnaChip’s specialty manufacturing expertise with NNFC’s robust RF technology. The two companies have targeted expansion into the emerging RF front-end module (“FEM”) foundry market.

ByAdministrator

More than 65% Smartphone RF Switches on SOI, Says Yole; Power Amps Next

The industry research firm Yole Développement says that more than 65 percent of substrates used in fabricating switches for handsets are SOI-based. This is a high-growth part of the market, putting up double-digit increases.

Like a standard SOI wafer, an RF SOI substrate has an active (“top”) layer on which CMOS transistors are built, with an isolating (“BOx”) layer under it.  The main difference is that the bottom “base” layer under the layer of isolation is a high-resistivity material. This reduces noise and interference, which helps the finished die reach its target performance in terms of signal integrity, handling RF power and integration density. SOI-based devices can reach a figure of merit for on-series resistance and off-equivalent capacitance (Ron.Coff ) below 200 fs (femtoseconds) with potential for further reduction. This directly relates to improved device performance and smaller die size.

At Semicon West SOI wafer manufacturer Soitec announced that its SOI technologies are now mainstream for manufacturing switches and antenna-tuners, key RF components for cell phones and tablets.

There are also new challenges as the industry moves from from 3G to 4G/LTE and further LTE Advanced using carrier aggregation. With SOI, designers can beat the demanding linearity requirements such as intermodulation distortion (IMD), going far beyond -110 dBm, thereby helping avoid interference between networks, says Soitec.

“RF SOI technologies enable the device integration, cost effectiveness and high performance needed for high-volume 3G and LTE applications,” explains Bernard Aspar, vice president, Communication & Power Business Unit at Soitec. “RF, with over 100 percent revenue growth last year, remains a strategic market in which we have been continuously investing for more than a decade.”

Aspar says that as the leading supplier of engineered wafers, Soitec is looking to catch the next growth wave in the RF market.

Based on recent demonstrations, Soitec sees power amplifiers as likely be the next RF components based on SOI. The technology enables highly tunable amplifiers to address multi-region requirements on a single platform. The RF SOI substrates also offer a path towards further integration, such as more mixed-signal and digital content.

Soitec explains that its approach is to offer a wide choice of engineered substrates, so that RF device manufacturers can choose the solution that aligns best with their market strategies – from low-cost GSM handsets to multi-band, multi-mode LTE smartphones and tablets.

ByGianni PRATA

SOI at IEDM 2010

The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies.

Here are summaries of key papers referencing work on SOI or other advanced substrates.

(Note: at the time of this posting, the papers are not yet available from the  IEEE Xplore website.  However, many are available from the Advanced Silicon Device and Process Lab at the National Taiwan University.)


Paper #1.2: Energy Efficiency Enabled by Power Electronics
Arunjai Mittal (Infineon)

In particular, see section 4, where the author addresses the huge energy savings that can be realized using variable speed motors. Infineon’s driver ICs (which take a logic signal output from a microcontroller chip in the control system, and provide the appropriate current and voltage to turn power devices on and off) are built on SOI. (See Infineon’s article in ASN7. Infineon and LS Industrial Systems started a JV in 2009 called the LS Power Semitech Co., which leverages this technology.)


#2.6: Engineered Substrates and 3D Integration Technology Based on Direct Bonding for Future More Moore and More than Moore Integrated Devices (Invited)

L. Clavelier, C. Deguet, L. Di Cioccio, E. Augendre, A. Brugere, P. Gueguen, Y Le Tiec, H. Moriceau, M. Rabarot, T. Signamarcheix, J. Widiez, O. Faynot, F. Andrieu, O. Weber, C. Le Royer, P. Batude, L. Hutin, J.F. Damlencourt, S. Deleonibus, E. Defaÿ, (CEA/LETI Minatec)

This paper deals with new generations of substrates and 3D integration techniques, based on direct bonding techniques, enabling future devices in the More Moore and in the More than Moore areas.


#3.2 : Planar Fully Depleted SOI Technology: A Powerful Architecture for the 20nm Node and Beyond (Invited)

O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst and S. Deleonibus (CEA/LETI Minatec)

The authors of this paper say that for 20nm node and below, they have proven that planar undoped channel Fully Depleted SOI devices are easier to integrate than bulk, non planar devices like FinFET. The paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed.


#3.3:  Anomalous Electron Mobility in Extremely-Thin SOI (ETSOI) Diffusion Layers with SOI Thickness of Less Than 10 nm and High Doping Concentration of Greater Than 1x1018cm-3

N. Kadotani,T. Takahashi, K. Chen,T. Kodera, S. Oda, K. Uchida*  (Tokyo Institute of Technology, *also with PRESTO)

This paper is the first to report carrier transport in heavily doped ETSOI diffusion layers. The authors found that electron mobility in the heavily doped ETSOI diffusion layer is totally different from electron mobility in heavily doped bulk Si. In other words, electron mobility is enhanced in thinner ETSOI diffusion layers (Tsoi>5nm), whereas electron mobility is degraded as dopant concentration increases when Tsoi is 2nm. The authors conclude that this information will be indispensable for the design of aggressively scaled ETSOI devices as well as 3D FETs.


#3.4:  Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX

O. Weber, F. Andrieu, J. Mazurier, M. Cassé, X. Garros, C. Leroux, F. Martin, P. Perreau, C. Fenouillet-Béranger, S. Barnola, R. Gassilloud, C. Arvet*, O. Thomas, J-P. Noel, O. Rozeau, M-A. Jaud, T. Poiroux, D. Lafond, A. Toffoli, F. Allain, C. Tabone, L. Tosti, L. Brévard, P. Lehnen #, U. Weber#, P.K. Baumann#, O. Boissiere#, W. Schwarzenbach+, K. Bourdelle+, B-Y Nguyen+, F. Boeuf*, T. Skotnicki*, and O. Faynot (CEA-LETI Minatec, *STMicroelectronics, #AIXTRON AG, +SOITEC)

For the first time, the authors demonstrate low-VT (VTlin ~± 0.32) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm ION and 245μA/μm IEFF at 2nA/μm IOFF and VDD=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32V to 0.6V for both nMOS and pMOS.


#8.1: Compact Modeling and Analysis of Coupling Noise Induced by Through-Silicon Vias in 3-D ICs

C. Xu, R. Suaya*, K. Banerjee (UC Santa Barbara, *Mentor Graphics)

This work presents compact models for cases without and with the high conductivity buried layer in dual-well bulk CMOS, which can be employed for keep away radius estimation. A comparative analysis of the coupling noise due to TSV in both dual-well bulk CMOS and PD-SOI is presented. The noise coupling for PD-SOI is much smaller than that of bulk CMOS due to the significantly shorter TSV height compared to that in bulk CMOS.


#8.2:  Large Signal Substrate Modeling in RF SOI Technologies

S. Parthasarathy, B. Swaminathan, A. Sundaram, R.A. Groves, R.L. Wolf, F.G. Anderson (IBM SRDC)

This paper describes a large signal high resistivity (HR) SOI substrate modeling methodology for high power circuit applications such as RF switches.  The authors show that using a varactor to model the BOX capacitor improves the harmonic distortion predictions from simulations for circuits in RF/Analog applications.


#8.5: MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress

N. Xu, X. Sun, W. Xiong*, C. R. Cleavelin, T.-J. King Liu (UC Berkeley, *Texas Instruments)

The authors made a detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors. The MuGFETs studied in this work were fabricated on (100) SOI substrates, with either <100> or <110> fin orientation.  They found that CESL-induced stress provides for the greatest enhancement in carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FET structures. Extracted carrier velocity values in short-channel FinFETs still largely depend on carrier mobility.


#11.1:  Dual Strained Channel Co-Integration into CMOS, RO and SRAM Cells on FDSOI Down to 17nm Gate Length

L. Hutin, C. Le Royer, F. Andrieu, O. Weber, M. Cassé, J.-M. Hartmann, D. Cooper, A. Béché*, L. Brevard, L. Brunet, J. Cluzel, P. Batude, M. Vinet, O. Faynot (CEA LETI Minatec, CEA-INAC)

The authors presented the first successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGeOI pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells.  Strained SiGe channels were found to present up to 92% long channel mobility improvement (Eeff=0.6MV/cm); the asset of effective mass reduction is highlighted for short channel pFETs. Moreover, the co-integration with sSOI nFETs leads to well-adjusted Vth,n and Vth,p with a single mid-gap gate for high performance applications, as shown by a 39% improvement of the ring oscillators propagation delay compared to the SOI reference.


#11.2: A Solution for an Ideal Planar Multi-Gates Process for Ultimate CMOS?

S. Monfray, J.-L. Huguenin, M. Martin*, M.-P. Samson, C. Borowiak, C. Arvet, JF. Dalemcourt*, P. Perreau*, S. Barnola*, G. Bidal, S. Denorme, Y. Campidelli, K. Benotmane*, F. Leverd, P. Gouraud, B. Le-Gratiet, C. De-Butet*, L. Pinzelli, R. Beneyton, T. Morel, R.Wacquez*, J. Bustos, B. Icard*, L. Pain*, S. Barraud*, T. Ernst*, F. Boeuf, O. Faynot*, T. Skotnicki (STMicroelectronics, *CEA LETI Minatec)

The authors demonstrate for the first time high-performant planar multi-gates devices integrated on an SOI substrate, with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm. They also demonstrate an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.


#12.1: 32nm High-density High-speed T-RAM Embedded Memory Technology

R. Gupta, F. Nemati, S. Robins, K. Yang, V. Gopalakrishnan, J.J. Sundarraj, R. Chopra, R. Roy, H.-J. Cho*, W.P. Maszara*, N.R. Mohapatra*, J. Wuu**, D. Weiss**, S. Nakib (T-RAM Semiconductor, *GLOBALFOUNDRIES, **AMD)

The authors present Thyristor Random Access Memory (T-RAM) as an ideal candidate for embedded memory due to its substantially better density-performance and logic process compatibility.  T-RAM technology with substantially better density-performance tradeoff  was previously reported was previously reported at the 130nm technology node. This paper is the first to report implementation details in a 32nm HKMG SOI CMOS logic process, with read and write times of 1ns and bit fail rate under 0.5ppm.


#12.3:  A Novel Low-Voltage Biasing Scheme for Double Gate FBC Achieving 5s Retention and 1016 Endurance at 85ºC

Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, W. Schwarzenbach*, O. Bonnin*, K. K. Bourdelle*, B.-Y. Nguyen**, C. Mazure*, L. Altimime, M. Jurczak (IMEC, *SOITEC, **SOITEC-USA)

A novel low-voltage biasing scheme on ultra-thin BOX FDSOI floating body cell is experimentally demonstrated. The new biasing scheme enhances the positive feedback loop. Therefore, the required VDS can be reduced to 1.5V while 5 seconds retention time can still be achieved at 85oC. Endurance up to 1016 cycles is shown.


#16.6: Realizing Super-Steep Subthreshold Slope with Conventional FDSOI CMOS at Low-Bias Voltages (Late News)

Z. Lu*#, N. Collaert*, M. Aoulaiche*, B. De Wachter*, A. De Keersgieter*, J. Fossum#, L. Altimime*, M. Jurczak* (*IMEC, #U. Florida/Gainesville)

The authors report the first experimental demonstration of a super-steep subthreshold slope (the smallest ever reported experimentally) with ultra-thin BOX FDSOI standard CMOS transistors. This work addresses the scaling challenge of continuing to reduce power consumption by lowering operation voltage.  Record steep SS of 72μV/dec for Lg=25nm and 58μV/dec for Lg=55nm are achieved with low voltages. The device also exhibits high ION (~100μA/μm), large ION/IOFF ratio of 108 with 0.5V gate swing for Lg=55nm MOSFETs and excellent reliability.


#18.3: Prospects for MEM Logic Switch Technology (Invited), T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott*, E. Alon (UC Berkeley, *Institute of Microelectronics/Singapore)

This paper provides an overview of recent progress in device design, materials/process integration and technology scaling toward achieving micro-electro-mechanical  (MEM) switches suitable for ultra-low-power digital IC applications.


#27.5: A 0.039um2 High Performance eDRAM Cell Based on 32nm High-K/Metal SOI Technology

N. Butt, K. Mcstay, A. Cestero, H. Ho, W. Kong, S. Fang, R. Krishnan, B. Khan, A. Tessier, W. Davies, S. Lee, Y. Zhang, J. Johnson, S. Rombawa, R. Takalkar, A. Blauberg, K.V. Hawkins, J. Liu, S. Rosenblatt, P. Goyal, S. Gupta, J. Ervin, Z. Li, S. Galis, J. Barth, M. Yin, T. Weaver, J. H. Li, S. Narasimha, P. Parries, W.K. Henson, N. Robson, T. Kirahata, M. Chudzik, E. Maciejewski, P. Agnello, S. Stiffler, and S.S. Iyer (IBM SRDC)

The authors present the industry’s smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate SOI based logic technology. With aggressive cell scaling, High-K/Metal trench lowers parasitic resistance while maximizing capacitance. Fully-integrated 32Mb product prototypes demonstrate state-of-the-art sub 1.5ns latency with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.


#34.2:  Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI

I. Ok, K. Akarvardar*, S. Lin**, M. Baykan^, C.D. Young, P.Y. Hung, M.P. Rodgers^^, S. Bennett^^, H.O. Stamper^^, D.L. Franca^^, J. Yum#, J.P. Nadeau##, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy (SEMATECH, *GLOBALFOUNDRIES, **UMC, ^U.Florida, ^^CNSE, #U. Texas/ Austin, ##FEI)

The authors have demonstrated high performance p-channel Si/SiGe stacked FinFETs with salient features including 1) high intrinsic mobility; 2) good interface quality without the need for a Si cap between SiGe and High-k; 3) low series resistance; 4) process-induced strain additivity; and 5) a convenient threshold voltage for high performance logic using a midgap metal gate. They also demonstrate a dual channel scheme for high mobility CMOS FinFETs.


#34.3: Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement

M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida*, and T. Numata (Toshiba Corp., *Tokyo Institute of Technology)

The authors found that short-channel mobility in SOI nanowire transistors (NW Tr.) is dominated by the strain induced in the NW channel. They enhanced NW strain by the stress memorization technique (SMT). In <110> NW nFETs, Ion on the same DIBL largely increases by SMT thanks to mobility increase and parasitic resistance reduction.  They conclude that stress engineering is highly effective for the performance improvement of scaled NW Tr.


#34.5:  Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape

P. Hashemi, J.T. Teherani, J.L. Hoyt (MIT Microsystems Technology Laboratories)

The authors present a detailed study of hole mobility for gate-all-around Si NW p-MOSFETs with conformal high-k/MG and various hydrogen annealing processes. The devices are fabricated along the <110> direction on (100) thin body SOI.  Increasing hole mobility is observed with decreasing NW width down to 12 nm. A 33% hole mobility enhancement is achieved relative to universal (100) at high Ninv.


#35.4:  A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices

D.Sarkar, S. Thijs*, D. Linten*, C. Russ**, H. Gossner**, K. Banerjee, (UC Santa Barbara, *IMEC, **Infineon Technologies)

The authors investigated the impact of strain on different ESD protection devices. It is shown for the first time that the ESD sensitivity to strain can vary substantially depending on whether the devices stressed are bulk or SOI and on the mode in which they are stressed.  investigated. SOI NMOS exhibits about 20% improvement in ESD robustness in GG mode. The authors conclude that strain will play an important role in optimization of ESD device robustness of advanced CMOS technologies.