Tag Archive RFID

ASN Celebrates a Decade of SOI News, Views and Commentary

April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.

Wow, were we precient.

Consider some of the topics we covered in that first edition, back in April of 2005:ASN10

Not bad!

ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.

The presentation is now posted on SlideShare (click here to see it).

It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.

If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.

We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)

Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.

Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.

And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.

In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.

So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.

The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.

I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.

In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.

With warm regards,

– Adele

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

Hitachi’s tiny mu-chip

Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity.

The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version of the world’s smallest RFID chip is based on SOI technology. The result is a chip so small, so thin, that it easily leaves the others behind by at least two generations.
How small is small? Consider it this way. The µ-chip that has been in mass production since 2001 measures 0.4mm on a side – so you could hide it comfortably under a grain of salt.
The newest generation µ-chip on SOI measures 0.15mm on a side – so you could hide about a dozen of them under that same grain of salt.

How thin is thin? The current generation is 60 microns thick – about three-quarters as thick as a piece of paper, which is typically about 80 microns thick. The new generation on SOI is only 7.5 microns thick – so a stack of 10 would still be less thick than a piece of paper.
For Hitachi, these SOI-enabled smaller dimensions translate into two very important advantages:
1. Substantially lower cost of ownership.
With SOI, each device is surrounded by insulator, preventing interference between devices and enabling higher integration on an even smaller area. With the smaller chips, more fit on a wafer – in this case as much as seven times as many. That makes for dramatically lower manufacturing costs – which could potentially enable the company to break the 5-cent barrier that analysts say is needed to really launch the RFID revolution.

2. The ability to embed the chips in paper.
This opens the door to a whole new realm of applications. Anywhere paper and security considerations intersect, the new µ-chip is a very attractive contender. The extreme thinness was achieved by completely removing the supporting silicon layer, leaving only the top silicon layer in which the circuit is fabricated, and the layer of insulation beneath it.

The µ-chip is being used for animal tagging in East Asia to ensure traceability in the food supply chain. (Courtesy of Hitachi America)

Lowering costs

Until now, cost has been a major impediment to large-scale RFID deployment. The current generation µ-chip plus antenna was selling in the 10- to 15-cent range. With the massive increase in productivity enabled by the smaller chip, Hitachi should be well positioned to bring prices down further.
Says Sarah LoPrinzi, BCC Research Analyst and author of “RFID: Technology, Applications and Market Potential” (August 2006), “Hitachi’s recent announcement of the next generation of µ-chips resolves some of the technical and economic chip manufacturing issues that have impeded the development of low cost RFID tags. In the RFID industry, the magical cost-per-tag is widely thought to be $0.05/tag. Once the $0.05 barrier is overcome, item-level inventory control becomes more realistic.”

Put it in the paper

The new, ultra-thin µ-chip opens the doors to a wider range of paper-based applications, acting as an “intelligent watermark”.

As Mark Roberti, editor-in-chief of the RFID Journal, told ASN, “The value in having an ultra-thin RFID tag is that companies can embed the tag in packaging materials for product authentication and anti-counterfeiting applications without worrying that the transponder will be so visible as to make the packaging unattractive.” Retail gift certificates, labels and other paper documents would benefit from enhanced security.

To help fight counterfeiting and improve supply-chain management, Winwatch of Switzerland has IP for embedding RFID chips such as the µ into the glass, hands or axis of high-end watches. (Courtesy of Winwatch)

An obvious application might seem to be banknotes, but this is probably not for the very near-term. While embedding the newest ultra-thin µ-chip in paper currency is now entirely feasible from a technical standpoint, there still remain issues for government and public debate regarding privacy and security in the supporting infrastructure design.

But with both businesses and governments looking for more reliable, cost-effective electronic solutions for managing supply chains and preventing fraud, the tiny µ-chip should be a major player.

* Concept: Read the technical description on the Hitachi website

Full use of SOI advantages enables small, thin, and low-cost RFIDs

A lead developer of Hitachi’s µ-chip explains the SOI benefits.

By using SOI, we could make an ultra-small RFID chip. In particular, its excellent isolation capability enabled successful miniaturization of the analog circuits in the front-end of the part. Also, BOX (Buried OXide) acts as an etch-stop layer in the self-controlled process, resulting in an ultimately-thin chip, which is as thin as 7.5 microns (including the multi-layered interconnection). A cross-sectional view of the ultra-thin chip is shown in the figure, where the chip is sandwiched in the antenna by using ACF (anisotropic conductive film). All of these contribute to the realization of low-cost, reliable, and widely-applicable RFIDs.

Honeywell & SOI: Military, Aerospace and Beyond

Honeywell has sent SOI by Jupiter and to Mars. Now its SOI rad-hard foundry services are charting new frontiers with the industry’s first 150 nm rad-hard, digital ASIC solutions and more.

Honeywell’s path runs parallel to commercial markets. Chips destined for space are increasingly facing the same performance vs. power issues of chips we find down here on the ground. Deep space probes are collecting, sorting, sifting and sending tens of gigabytes of data and images back home daily. And in our interconnected world, every one of us depends on satellites every day. Read More

SOI has made Hitachi’s newest”µ-Chip” the world’s smallest

• SOI has made Hitachi’s newest”µ-Chip” the world’s smallest, thinnest RFID IC chip ever. SOI prevents interference between devices, enabling higher integration on a smaller area, increasing the number of chips fabricated on a single wafer and increasing productivity by more than four times. At 7.5-µm thick, this SOI-based chip is 1/8th the thickness of its bulk predecessor. This was achieved by the complete removal of the silicon layer on the reverse side of the SOI substrate on which the circuit is fabricated.