Tag Archive RISC-V

ByAdele Hars

QuickLogic ultra-low power eFPGA on GF’s 22FDX FD-SOI and in PULP/RISC-V SoC

(Courtesy: PRNewsfoto/QuickLogic Corporation)

Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now.

ArcticPro is the industry’s first eFPGA offering for GF’s 22FDX® process (btw they’ve been shipping it in volume for GF’s 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device’s functionality in the field.

(Image courtesy: QuickLogic)

QuickLogic has also announced that the technical university ETH Zurich  will integrate QuickLogic’s ArcticPro technology onto the university’s PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF’s 22FDX process node. They will develop an SoC integrating ETHZ’s open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption.

“The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” said QuickLogic CTO Dr. Timothy Saxe. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”

ETH’s PULP platform with the fully integrated eFPGA is expected to be available Q1′ 2019.

QuickLogic is part of GF’s fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.

ByAdele Hars

Silicon Valley FD-SOI 2018 Training Day is April 27th – Don’t Miss It!

Following the immense success of last years FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up.

ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design.

You’ll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices.

Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond.

The design examples will cover basic building blocks through SoC implementations. A global Q&A session will close the day.

Here’s a little more info on how the day will unfold. Click on the slides to see them in full screen.

Morning sessions

FDSOI-specific design techniques for analog, RF and mmW applicationsAndreia Cathelin, Fellow, STMicroelectronics

Quick preview from Andreia Cathelin’s FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)

Andreia Cathelin is ST’s key design scientist for all advanced CMOS technologies, and is arguably the world’s leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She’ll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance.

Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz ApplicationsFrank Zhang, Principal Member of Technical Staff, GlobalFoundries

Quick preview from Frank Zhang’s FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)

Frank Zhang has designed chips using GF’s 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements.

Afternoon sessions

Energy-Efficient Design in FDSOIBora Nikolic, Professor, UC Berkeley

Quick preview from Bora Nikolić’s FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)

Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team’s RISC-V chip was cited as one of Dr. Cathelin’s “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He’ll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley’s latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI.

mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies – Sorin Voinigescu, Professor, University of Toronto

Quick preview from Sorin Voinigescu’s FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)

Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He’ll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he’ll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he’ll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies.

Sign Up Now!

With over 100 attendees filling every chair in the auditorium, last year’s training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”

2018 will be no different – except that it’s sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks.

Here’s key info you need to sign up. See you there!

What: SOI Consortium’s FD-SOI Training Day

When: 27 April 2018, 7:30am – 5pm.

Where: Crowne Plaza San Jose, Milpitas CA (parking is free)

Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)

How to sign up: Click here to go directly to the registration site.