Good news: there are far fewer bigoted extremists out there when it comes to FD-SOI vs. FinFETs. People want the best technology for their application. It’s that simple. That’s a key piece of news from the updated survey by Dan Hutcheson, CEO of VLSI Research, which he presented in the afternoon session of the SOI Consortium’s 2018 SOI Symposium in Silicon Valley
The afternoon then featured presentations by foundry partners, which I’ll cover here.
Also in the afternoon were presentations by wafer-maker Simgui, some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion. I’ll cover those in Part 3 of this series.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it.
The presentations are starting to be posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
A couple years ago at the annual SOI Symposium in Silicon Valley, Dan Hutcheson presented results of a survey he did (ASN covered it – you can still read about it here). At the 2018 event, he presented an update, which is now posted. You can get it here.
The FD-SOI roadmap and IP availability are no longer issues for decision makers, he found. The 14nm branch – do you go FinFET or FD-SOI? – is gone. “Fins and FD are complementary,” he observed. Most people said they’d consider using both and running two roadmaps, choosing whichever technology is appropriate to a given design.
From a transistor viewpoint, the top reasons to choose FD-SOI is that it’s better for analog and has lower leakage/parastics. It’s perceived as better for complex, high mixed-signal SoCs, and especially for RF and sensor integration. In fact, people see RF as the new mixed-signal, wherein FD-SOI is uniquely positioned for 5G and mmWave.
From a business viewpoint, FD-SOI is perceived to have real advantages. In particular, FD-SOI wins when it comes to keeping down design costs, manufacturing costs and time-to-market. IoT is still the hottest target market for FD-SOI, to which he adds high growth expected in automotive and medical.
With 20 tape-outs in 2018, Samsung is seeing an acceleration in its FD-SOI business. “The trend is healthy,” said Hong Hoa, SVP of the company’s foundry business. FD-SOI, he continued, is on a “differentiation path.”
Samsung’s 28nm FD-SOI process, called 28FDS is at full maturity with very strong yields. They’re seeing more customers and a wider range of applications. The design infrastructure, silicon-verified IP and methodologies are also all mature. They have optimal implementation and verification guidelines for body bias design, a body bias memory usage guide, and a body bias generator integration guide. The process supports Grade 1 automotive, and will be qualified for Grade 2 in a few weeks.
FD-SOI, Hoa reminded the audience, offers superior RF performance compared to both planar bulk and 14nm FinFET. The Samsung strategy is to first provide a base for for the FD-SOI process, then add RF and eMRAM. The base for 28nm was done in 2016; they added RF in 2017 and eMRAM this year.
The Samsung platform for IoT applications integrates both RF and eMRAM to support multi-function needs in a single platform. Lead customers are already working with eMRAM in their designs, he added. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it on YouTube here.)
The basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDSplatform will be ready by the end of this year, and eMRAM beginning in 2019.
With design wins from 36 customers underway, 12 of which are taping out in 22FDX (GF’s 22nm FD-SOI process) this year, the market has validated FDX for differentiation, said GF SVP Dr. Bami Bastani. And indeed, designers are using it for a wide array of applications across North America, Europe, Asia/Pacific and Japan.
Customers in the North America are designing in 22FDX for NB-IoT, industrial, RF/analog, mobile, network switches and cryptocurrency applications. In Europe, it’s more or less the same plus automotive/mmWave, optical transmission, wireless BTS and AI/ML. In Asia Pacific/Japan the mix is similar to Europe.
Bastani sees the three big enablers as the the strengths of the roadmap, the ecosystem and multi-sourcing from Dresden and Chengdu (where they’re already equipping the cleanrooms). He also tipped his hat in acknowledgment to the partnership with FD-SOI wafer supplier Soitec, noting that they have gone the extra mile to match GF’s requirements.
So that was the first part of a great afternoon. As mentioned above, my next post (part 3) will cover a very informative presentation by wafer-maker Simgui on the markets in China, plus talks by some innovative start-ups leveraging FD-SOI for custom SoCs and the final panel discussion.
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.
Here’s a recap of what the Cadence folks said. (I’ll cover the Synopsys and Silvaco presentations in my next posts.)
At the Shanghai FD-SOI Forum. Dr. Qui Wang, VP & Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.
In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.
To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.
Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World — Cadence EDA & IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.
He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.
His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow).
Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)
Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.
For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry’s PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.
And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).
Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.
Synopsys’ custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE® golden-accuracy circuit simulation, Custom Compiler™ visually-assisted layout automation, StarRC™ gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT, connectivity, mobile computing and automotive. (Read the full press release here.)
“Samsung Foundry’s certification of Synopsys’ custom design platform is important to our mutual customers developing complex designs,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity.”
Custom Compiler’s user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS PDK in the industry-standard interoperable (iPDK) format.
“Samsung Foundry’s 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “We worked with Synopsys to certify Synopsys’ custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development.”
Day 2 of the recent SOI Workshop in Tokyo was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.
It was a really full day, so the recap in this post covers about half of the Day 2 presentations. My next post will cover the rest of them. (In case you missed it, Day 1 was covered in my previous post – you can read it here.)
Another Sony GPS Win!
The day kicked off with a talk by Sony GM Kenichi Nakano, entitled Sony Semiconductor Low-Power IoT Solution. He reminded the audience that Sony started looking at FD-SOI in 2013, and announced at ISSCC last year (the paper’s available from the IEEE – click here). Power, he said, is everything.
And that low-power GPS in Casio’s latest Pro Trek Smart watch, the WSD-F20? It’s based on Sony’s new CXD5602 – and that’s on FD-SOI, to which they give largely give credit for the >75% reduction in power from the previous generation.
Samsung: Surf’s Up!
FD-SOI is mature, and they’re ready to surf it, said Principle Designer at Samsung Foundry Marketing, Yongjoo Jeon. But, he added, they’ll continue to evolve it.
Covering a wide range of applications, he sees FD-SOI as a key in the 4th industrial revolution. In terms of power/performance, the “…excellent short channel effect enables better performance and lower power than bulk technology.” And, “Body bias enhances further performance [FBB – forward body bias] and power reduction [RBB – reverse body bias].”
That provides some unique benefits, he pointed out.
in automotive, it’s safety: the physical dielectric isolation is almost free from SER (soft error rate)
for analog/RF, the long channel gain is more significant with excellent noise immunity
for every application, lower doping enhances variation immunity
Samsung reached high yield (defect density D0<0.2) very quickly, and ramped rapidly to mass production (which is where they are with NXP as of Q1/17). This, he said, shows the maturity of their 28FDS FD-SOI technology.
Then he turned to design. Samsung (which does btw, offer Design Services) has an IP portfolio that is wide and deep, with a strong, well-established reference flow, supported by both Cadence and Synopsys.
In terms of RF, 28FDS has better fT than 28nm bulk. The physical isolation of the SOI structures enables a “no guard ring” approach, and specific RF offerings include LDMOS for PAs (power amplifiers). Samsung is supporting a new mm-Wave Pcell, which will be added in the V1.1 PDK.
Samsung is also adding eMRAM (embedded magnetoresistive RAM – it’s already yielding at 60%), as they see 28nm is probably the last node for eflash. “We’re very proud of these technologies,” he said.
Samsung’s next generation of FD-SOI will be 18nm, which provides a 20% increase in performance, a 40% decrease in power, and a 30% reduction in logic area.
Cadence EDA & IP Update
FD-SOI enablement usually means PDKs and tech files, noted Jonathon Smith, Director of Strategic Alliances at Cadence. But for deep benefits, you need to work with the foundries on characterizing libraries, and that’s just what Cadence is doing with both Samsung and GlobalFoundries, he said.
He gave a very frank and interesting talk entitled Enabling an Interconnected Digital World: Cadence EDA & IP Update. IoT, he noted, will include a lot of mixed-signal and complex packaging. Customers need modular reference flows, and they want flexibility and multiple foundry nodes. For FD-SOI, Cadence has been working on PDK enablement, tool readiness and design tools for several years. There is one database for both digital and analog.
For Samsung’s 28FDS, everything from logic synthesis to sign-off and analog tools are certified. In fact Cadence recently announced its custom/analog tools and full-flow digital and signoff tools have achieved Samsung certification for the PDK and foundation library (see the press release here).
For GlobalFoundries 22FDX, Cadence is certified across the entire design flow, and the reference flows are downloadable.
In terms of IP, he acknowledged that what Cadence has is not very extensive, so they are working with both partners and competitors. However, he did point out that their Tensilica IP for automotive is gaining traction: it is used in the Dreamchip ADAS chip fabbed on GF’s 22FDX, for example.
Wait, There’s More!
Day 2 in Tokyo was really packed with excellent presentations – too much for just one post. See Part 2 of my Day 2 coverage for highlights from Leti, GlobalFoundries, Soitec, MIPS/Imagination and more.
Over a hundred chip designers packed the room for the SOI Consortium’s recent FD-SOI Design Techniques Tutorial Day. Five professors and scientists from top institutions covered design techniques with real examples in digital, mixed-signal, analog, RF, mmW and ULV memory.
Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”
Many of the questions pertained to body biasing, which prompted STMicroelectronics Fellow and Professor Andreia Cathelin to state what may well have been the take-away of the day. “Body biasing is not an obligation,” she said. “It’s an opportunity.”
The tutorial, sponsored by both Samsung and GlobalFoundries, was hosted by Samsung at their San Jose headquarters. But as this was a paying event, the presentations are only available to those who attended. Having had the good fortune to attend, I can give you a quick recap of some of the highlights.
Professor Cathelin set the stage with a basic overview of FD-SOI design for analog, mixed-signal and mmW.
FD-SOI is a perfect match for the many up and coming SOCs that are often half analog and/or RF and mmW. She explained how FD-SOI makes the analog designer’s life much easier (no small feat, since analog can seem rather like blackbox magic to those on the digital side). FD-SOI improves: performance (even at high frequencies), noise, short device efficiency and brings in a new very efficient transistor knob through the Vt (threshold voltage) tuning range. She also explained and gave numerous real examples implemented in ST’s 28FDSOI on how:
For mmW design, the transistor should operate at Lmin, and hence you get excellence performance in terms of both transition frequency (Ft – set by the technology node) and maximum frequency (Fmax – what the designer can really get in the gain vs. speed trade-off). This can be conjugated with the fact that the back-end of line, despite the very fine nm node, takes advantage of the SOI features and brings in very decent quality factors.
For mixed-signal/high-speed design, she showed how and why FD-SOI gives you improved variability, a fantastic switch performance, and reduced parasitic capacitance. All these permit state of the art results in high-speed data converters, or, for example, lower frequency implementations which do not need any specific calibration for best in class linearity and ENOB (effective number of bits).
She also presented details on the CEA-Leti electrical models which are now the reference stand point (Leti-UTSOI2) for any FDSOI technology, and are implemented in several industrial Design Kits such those from ST.
Next on tap was a very lively talk with almost 60 slides by Professor Sorin Voinigescu of U. Toronto. He focused on how to use the main features of FD-SOI for efficient design of RF, mm-wave and broadband fiber-optic SOCs. We’re talking high-speed/high-frequency here, and he had real examples of chips fabbed in ST’s 28FDSOI and some simulated in GlobalFoundries’ 22FDX technology.
He examined layout issues and gave measurement tips and tricks, noting that there are a lot of things you can do in FD-SOI that you can’t do in bulk. It’s also easier to get high linearity in FD-SOI – yet another reason that he really likes it. Plus he sees it as competitive in terms of scaling even past 7nm.
Professor Joachim Rodrigues of Lund University in Sweden (the largest university in Scandinavia) talked about Design Strategies for ULV memories in 28nm FD-SOI (ST’s FD-SOI technology). Noting that SRAMs eat a lot of area in an SOC, he first proposed a standard cell-based memory (SCM) in 28nm FD-SOI that cut memory area by 35% and reduced leakage by 70%.
He then talked about other chips he and his team have presented at the world’s top chip conferences, including an ultra-low voltage (ULV) SRAM. For that chip they lay claim to having the best write performance in ULV in sub-65nm (15MHz at 240mV), and the best performing read capability across all technologies (30MHz at 240mV). In each case, he explained the fundamental design considerations, concepts and trade-offs.
Professor Borivoje “Bora” Nikolic of UC Berkeley is an expert in body-biasing for digital logic. He and his team have designed ten chips in ST’s 28nm FD-SOI, and they’re now working on their 8th generation of energy-efficient SOCs. During his 90-slide (!) tutorial, Energy-Efficient Processors in 28nm FDSOI, he covered: digital logic (including implementation and adaptive tuning of cores for optimal energy efficiency); SRAM and caches (design scenarios and results compared to bulk); supply (generating, switching and analog assists); back bias (how it’s generated and how to use it). He finished with (60 slides of!) design examples and the results they got for power (including adaptive voltage scaling) and performance. He said to be on the lookout for upcoming publications on (even more!) chips, as well as new work on 22nm designs.
Even if you don’t know anything about mixed-signal design, you can walk away from an hour-long lecture by Professor Boris Murmann of Stanford with a good understanding of what it’s all about. In his talk, Pushing the Envelope in Mixed-Signal Design Using FD-SOI, he explained how a mixed-signal person thinks about FD-SOI, and how the different metrics and sweetspots vary depending on what you’re working on. From there it was the deep dive, as he got into the heart of his talk: simulated transition frequency vs. gm/lD. He explained that while some things might seem counter intuitive (like long channels are more efficient for very low Ft requirements), it’s all related to electrostatics. It’s not yet well explained in the literature, he said, but it should be a big deal. And he explained why with FD-SOI, you don’t have to design for the worst case. He then talked about where he sees things going – he sees a very bright future indeed for FD-SOI and analog as computing moves into very low-power neural networks. In the end, he said, it all boils down to the FD-SOI performance benefits with respect to better gate control. This translates into “significant improvements” for many mixed-signal/RF building blocks.
All in all, it was a really terrific day. BTW, this tutorial day followed a full-day FD-SOI Symposium in Silicon Valley. Click here to read about that.