Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It’s in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance).
If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you’ll want to share this piece with them right away.
Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What’s more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don’t worry that this might be too technical: Sellier’s writing is thoroughly accessible (and engaging!) for anyone in the industry.
He starts with the wafer history, then quickly moves on to the features from the designer’s standpoint. And he puts it all in a business perspective. I can’t recommend this piece enough – even if you think you know everything already yourself, you’re sure to learn something new.
“GlobalFoundries, TowerJazz, TSMC and UMC are expanding or bringing up RF SOI processes in 300mm fabs in an apparent race to garner the first wave of RF business for 5G, the next-generation wireless standard,” writes Mark Lapedus of Semiconductor Engineering. His recent piece, RF-SOI Wars Begin, explains why demand across the supply chain is currently tight.
Rest assured, the supply situation is being addressed fast. By next year, 300mm-based RF-SOI manufacturing (vs. 200mm) will increase from 5% to 20%. But with insatiable end-user demand for greater throughput, overall RF-SOI device demand is increasing in the double-digit range, so 200mm-based manufacturing is also expanding fast.
SOI wafer manufacturer Soitec has 70% of the RF-SOI wafer market share. The other RF-SOI wafer manufacturers – Shin-Etsu, GlobalWafers and Simgui – all use Soitec’s RF-SOI wafer manufacturing technology.
This is an excellent, comprehensive piece, that clearly explains the complexities of the markets, the devices, the manufacturing and the supply chain. It’s a highly recommended read.
BTW, the SOI Consortium is organizing a 4G/5G SOI supply chain workshop during Semicon West (July ’18). Sign up or get more information on that under the Events tab here on the consortium website.
Of course, here at ASN, we’ve been covering RF-SOI for over a decade. You can use our RF-SOI tag to access most of the pieces we’ve done over the years.
With the great news about FD-SOI foundry offerings from Samsung, ST and now GlobalFoundries, plus the IP availability, the wafer suppliers have chimed in to remind the ecosystem they’re ready to ramp (and have been for a number of years!). So the wafers are ready (and they truly are amazing), the processes ensuring high yield are in place, and high-volume capacity is ready to roll. Most recently in the wafer news, top-10 equipment supplier Screen Semi Solutions has joined the ecosystem (press release here) with wafer cleaning processes that ensure and maintain the requisite wafer uniformity in high-volume FD-SOI wafer production.
The industry-standard process for making all the different flavors of silicon-on-insulator (SOI) wafers (FD-SOI, RF-SOI, power, photonics, etc.) is Soitec’s Smart CutTM technology (you can learn about how it works here). Invented at Leti and industrialized by Soitec, Smart Cut made its world debut at Semicon West 20 years ago (!!) in 1995.
But for FD-SOI, the SOI wafers needed to meet new exigencies of extremely thin and uniform top silicon and an extremely thin insulating (aka Buried Oxide, or BOx) layer. Consider this: uniformity of the top silicon layer of Soitec FD-2D wafers (that’s the wafer product name) is guaranteed to within +/-5Å at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. Meeting this requirement is not new: Soitec announced they were ready for industrialization with this level of uniformity back in 2010.
As ST’s godfather of FD-SOI, Thomas Skotnicki, noted at Leti Days in Grenoble a few weeks, Soitec made even greater strides in the wafer requirements for the 14nm node. The FD-SOI offering just announced by GF is referred to as 22nm, but that really means a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end.
Here’s what Paul Boudre, CEO of Soitec had to say about the GF announcement: “GlobalFoundries’ announcement is a key milestone for enabling the next generation of low-power electronics and we are very pleased to be GlobalFoundries’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology. With our two fabs and our worldwide licensing strategy, the market will enjoy all of the SOI wafers it needs for strong adoption. The markets we are addressing with this product will be key contributors to Soitec’s growth.”
For a number of years now, Shin‐Etsu Handotai (SEH), the world’s largest maker of silicon wafers, has been saying that they’re meeting the specs for FD-SOI wafers, too (read about that here), and can quickly expand capacity to meet rising demand. SEH is a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers. They’ve been making SOI wafers since 1988, and in 1997 first introduced SOI wafers produced using Soitec’s Smart Cut technology. (And of course Soitec and SEH continue their long-standing collaboration – read about that here.)
So with the GF announcement, Nobuhiko Noto, general manager of SOI Division at SEH, said, “SEH welcomes this development, bringing FD-SOI products to the industry, and we look forward to the continuation of our work in extending the global supply chain for FD-SOI. We are very glad to be engaged in supporting the growth and development of the FD-SOI market, own FD-SOI wafer supply.”
So no worries about wafer supply. As Dr. Handel Jones, CEO of IBS notes, “Multi-source supply chain for substrates has been established, and wafer volumes can potentially be one million per year and more in the future. We are confident that Soitec and its licensing to supply the substrates required to allow FD-SOI wafer volumes to reach their potential.” (You can read Dr. Jones’ ASN posts here.)
At Semicon West, Soitec and Screen Semiconductor Solutions announced they have jointly developed a process to ensure atomic-scale uniformity of ±5 angstroms across the surface of all 300-mm FD-SOI wafers at the high-volumes the industry needs.
Maximizing FD-SOI production yields is of course critical to meeting worldwide market demand.
“Our strategic partnership with Screen enables us to produce ultra-thin FD-SOI substrates that meet chip makers’ challenging requirements of atomic level resolution in high volume manufacturing. Our FD-SOI wafers are already qualified by a number of foundries,” said Christophe Maleville, senior vice president of Soitec’s Digital Electronics Business Unit. “We are extremely pleased to see such high support from Screen on FD-SOI manufacturing and we are looking forward to finalize our on-going efforts on 14nm FD-SOI node.”
“Screen is proud to collaborate with Soitec on meeting this advanced technical challenge and enabling FD-SOI technology to reach high performance levels,” said Screen CTO Dr. Olivier Vatel.“Our high-productivity cleaning systems are available and ready for the FD-SOI ecosystem. As an industry leader, we will continue to deliver world-class products that contribute to our customers’ market success.”
Screen’s single-wafer cleaning equipment, the SU-3200, delivers the industry’s best productivity by using a perfect balance of high-speed cleaning capacity and highly stable processing. It has multiple process chambers, allowing each wafer to be treated individually with its own dedicated recipe based on incoming layer thicknesses, the desired surface condition to be achieved and a predictive etch model. Key advantages of the system include highly uniform chamber-to-chamber processing and cycle times for robust results, tight control of layer thicknesses, the elimination of defects and metal contamination and high productivity enabled by a versatile chemical-supply system.
So it’s all systems GO!
Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.
If you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.
Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.
FD-SOI foundry offer
FD-SOI IP offer
FD-SOI design experience
Advantages and opportunities when designing with FD-SOI — Moderator: Dan Nenni, SemiWiki
If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.
This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.
For the SF event – here’s the key information:
FD-SOI and RF-SOI Forum
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
SOI-3D-Subthreshold Microelectronics Technology Unified Conference
6-9 October 2014
Westin San Francisco Airport, Millbrae, CA
Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.
The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.
The 2014 edition of the conference already promises a rich content of high-level presentations.
The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.
Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.
On the same webpage, more information is given about the various dedicated sessions.
There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.
The Committee will review papers submitted by May 26 in the three following focus areas of the conference:
Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.
The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.
Paper submission deadline: 26 May 2014
Notification of acceptance: 23 June 2014
Short course date: 6 October 2014
Conference date: 6 – 9 October 2014
More details are available on the S3S website.
Christophe Maleville has been Senior Vice President of Soitec’s Microelectronics BU since 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as Vice President, SOI Products Platform at Soitec, working closely with key customers worldwide. He has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from the Grenoble Institute of Technology and obtained an Executive MBA from INSEAD.
Advanced Substrate News (ASN): With the recent news that Samsung has joined the ranks of foundries offering high-volume 28nm FD-SOI, can you tell us why customers are turning to FD-SOI?
Christophe Maleville (CM): The short answer is that they consider FD-SOI provides a much better combination of power consumption, performance and cost than any alternative for the technology node they target.
At 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node. And for some products at least, using this enhanced 28nm is actually a better choice than going to the next node.
Then 20nm FD-SOI (also called 14FD) will provide the kind of performance and energy efficiency promised by 16nm/14nm FinFET, at a lower cost than even 20nm planar bulk CMOS.
ASN: Who are the wafer suppliers and what kind of capacity is there?
CM: There are three major suppliers serving the FD-SOI market: Soitec, Shin-Etsu Handotai (SEH) and SunEdison (formerly MEMC). SEH is the world’s biggest producer of silicon wafers. Soitec is the world leader in SOI wafer manufacturing. SunEdison has been supplying SOI wafers for over a decade. SEH and Soitec use Soitec’s Smart CutTM manufacturing technology. However, each company fine-tunes the technology to meet to its customers’ specifications.
For our part, I can add that Soitec has two distinct production sites. We source the raw bulk base and donor wafers (from which the FD-SOI wafers are fabricated under our FD-2D product name) from a diverse group of suppliers, which enables us to optimize the quality of our wafers, combining the best wafers for donor and handle. We are converting capacity at our plants in France and Singapore to meet expected FD-SOI demand.
The industry’s current installed capacity is in the range of one million 300mm SOI wafers/year. However, the wafer suppliers are ready to expand capacity to meet market demand, so we could easily reach two million in well under a year, and continue ramping rapidly from there. It’s perhaps worth understanding that the equipment and materials needed to manufacture SOI wafers are standard industry hardware and materials – there are no exotic parts to the manufacturing equipment nor rare materials that could cause bottlenecks in the processes we use to manufacture the SOI wafers.
ASN: FD-SOI wafers are known to have very stringent requirements. Can you review those here?
CM: SOI wafers are subject to many of the same criteria as other advanced wafers, such as flatness and defectivity. The additional parameters for FD-SOI wafers, which require tight control, are:
The thickness of the top silicon of the SOI wafers (denoted as TSOI) we provide ranges from 10 to 16nm, depending on customer requirements and node. The top silicon essentially “pre-defines” the channel. But, it’s important to remember that the starting thickness of the top silicon in the wafer has to be a little thicker than you’ll find in the processed device, as a few nanometers of top silicon is etched away during device processing. So in a TEM of a 28nm FD-SOI transistor, you might see TSOI of 7nm, but the wafer that it started on would have had top silicon of 12nm, to accommodate the 5nm that would be etched away during processing.
In FD-SOI, the BOX layer is actively leveraged in back biasing, wherein you’re essentially creating a second (“back”) gate. This makes the parameters of the BOX layer especially important for ultra-low power operation.
ASN: Why do the wafers have to be so uniform?
CM: With respect to the top silicon uniformity, uniform thickness is crucial to controlling transistor threshold voltage (Vt) variability. The top silicon uniformity of Soitec’s FD2D wafers is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. For the BOX thickness, we can offer thicknesses ranging from 10nm to 25nm, again depending on the customer’s approach. Technology’s like ST’s UTBB (ultra-thin body and Box) leverage very thin BOX for body biasing, which gives them a big edge in performance and low-power.
ASN: Are suppliers really ready to produce these wafers in high volumes?
CM: Yes, at Soitec we announced that we were ready for FD-SOI wafer volume back in 2012. Having met the specifications, we focused on offering good yields to our customers. In fact, the yield for Soitec’s FD-2D substrates is already reaching the yields we have for our wafers for partially-depleted SOI, which we’ve been selling for over a decade. This was critical to our clients, in order for them to have a fully-qualified 28nm FD-SOI process using wafers from Soitec and other suppliers. The results that customers have demonstrated in terms of variability (especially for Vt distribution, which is closely linked to wafer uniformity) and the electrical results show the wafers fully meet their production requirements. Smart CutTM technology enables us to manufacture according to these stringent requirements, and our years of experience let us move into high-yield, high-volume FD-SOI wafers at the right cost and at the right time for the market.
ASN: Can wafer suppliers adapt to the fluctuations in demand seen in very high-volume markets?
CM: The SOI ecosystem is already familiar with the mobile market, which in terms of volumes is currently the world’s biggest market – and certainly is volatile. SOI wafers are widely used in RF, particularly in RF switches, where over 70% of the devices for smartphones are built on SOI. While wafers for RF have some specific parameters, generally speaking the FD-SOI wafers are produced using similar technology, flow and logistics as our SOI wafers for RF – so for us, it’s just another segment of the mobile market.
ASN: Some say that managing buffer wafer stocks would be too complicated for the foundries – is that true? Can you explain briefly how the wafer supply contracts are typically structured?
CM: The SOI supply chain is no different than the bulk supply chain. As such, the structure of the wafer supply model is similar to supply chains in other industries. The foundries don’t have to fully own and manage a costly buffer stock of wafers. In the case of large customers, they typically negotiate a supplier-managed inventory dedicated to their needs, and they only pay when they actually consume parts from this stock. This kind of buffer also helps smooth out possible rapid fluctuations of the demand.
ASN: For its latest report (which found that FD-SOI is the most cost effective approach for the 28nm an 14nm nodes), IBS uses the figure of $500/wafer. Is that realistic?
CM: While of course pricing depends on commercial negotiations, 500USD in volume for 28nm FD-SOI wafers is definitely a sensible budgetary price: conservative and achievable. And starting at the 28nm node, as IBS points out, using SOI wafers results in similar cost for processed wafer when compared to typical 28nm bulk reference – a phenomenon that gets even better with scaling to 14nm. And although the specifications for the 14nm wafers are more exigent, we confirmed that substrate cost increase will not exceed 10%.
ASN: What about the future – will the wafers be able to meet the specs for the 10nm market? What about the move to 450mm wafers?
CM: ST has indicated a 3-node FD-SOI roadmap: 28nm-14nm-10nm. Working with our partners, we’ve shown that from the perspective of the wafer specs, we can fully comply with the parameters required to support this. For example, we have engineered strained silicon that meets the 10nm node specifications for boosting mobility – there are no show stoppers here. In terms of 450mm, while it seems unlikely that the move is imminent within the next few nodes, we are full participants in the industry’s R&D efforts, and have demonstrated that with our Smart Cut technology using the standard toolset found in CMOS FEOL, we can produce 450mm versions of our FD2D wafers, when and if the need arises. We’re ready whenever the industry is.
(Courtesy: SEH, weSRCH)
A presentation by Shin‐Etsu Handotai (SEH, the world’s largest wafer supplier) detailing the company’s line-up of wafers for FD-SOI and SOI-FinFET is now available on weSRCH (click here to access it).
SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) In 2012, the two companies extended their licensing agreement and expanded their technology cooperation.
The SEH presentation on weSRCH was presented in Shanghai in October 2013. The company reiterated that it has achieved the quality, has the requisite experience, and has enough factories for rapid expansion.
FD-SOI could be the “tipping point” for SOI, supply chain expert Bill Kohnen indicated in a presentation at the Semiconductor Technical Purchasing Conference last fall. (See his ppt here.) He suggested, “Purchasing and Supply Chain Organizations at Foundries and Device Manufacturers that need SOI wafers need to closely monitor the supply chain as demand resulting from FD-SOI applications may be the tipping point for capacity issues.” He concludes that the industry consortiums will be helpful in avoiding a “bullwhip effect”.
Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. hosted an “SOI Technology Summit” in Shanghai, China.
Executives of leading companies, universities and institutes, covering all the segments (substrate, design, manufacturing, EDA, IP, etc.) gathered to discuss the solutions to scaling challenges and the market opportunities for FD-SOI in China.
Handel Jones from IBS presented the IC market overview (available here) and detailed the cost difference between the different available technologies. He made the point that FD-SOI is cost competitive at 28nm and has the advantage at 20nm.
David Jacquet from ST highlighted (available here) the design benefits of back-biasing (the FD-SOI version of body biasing), which is only going to be available in FD-SOI technology since it cannot be implemented in planar bulk or FinFET in an effective manner. ST showed how back bias can provide real time optimization of the power-performance trade off and therefore give the most efficient mobile power saving results.
XMC’s Simon Yang gave a foundry manufacturing perspective on FD-SOI technology (available here), confirming that FD-SOI has a lot of advantages. In particular, it is perceived as the simplest way to enter the realm of fully depleted technologies. Also, he emphasized the necessity that the cost of FD-SOI be lower than competitive technologies, which aligned well with Handel Jones’ cost analysis. The wafer manufacturers also confirmed that the substrate price will enable the technology to be lowest cost.
Zhongli Liu, a very highly respected professor at IM CAS urged the Chinese IC industry to see the golden opportunity in FD-SOI technology. He detailed the technology benefits with well-chosen case studies (available here) and concluded that FD-SOI has broader markets since it has perfect features to match the needs of the mobile applications.
Rama Divakaruni from IBM presented a compelling talk on the IBM scaling path at 14nm, 10nm and 7nm (available here). For calculation-intensive applications such as servers, IBM is developing a 14nm FinFET on SOI with eDRAM that provide significant value propositions. Rama reminded the audience that IBM has developed both FD-SOI and FinFET on SOI, the latter being more adapted for IBM’s applications. However, depending on application and design style FD-SOI might be better suited.
SEH, SunEdison and Soitec presented wafer specifications and available capacity for RF-SOI, FD-SOI and FinFET on SOI. They showcased RF-SOI to demonstrate that SOI can be a mainstream solution meeting the cost and volume of the market demand.
Panel discussions at the end of the workshop were passionate regarding China’s opportunity to develop FD-SOI capacity, which could be a great accelerating factor for the China IC industry. This would require a commitment from foundries and design companies, which all agreed looks like the right thing to do.