If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.
Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI) in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.
Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.
In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents. This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.
So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.
For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.
In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.
One example of how effective our IP policy is came about in 1997 when we contracted with Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.
Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.
The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.
Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.
Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.
The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level. We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.
In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.
The world’s largest maker of silicon wafers, Shin‐Etsu Handotai (SEH) says it’s meeting the specs for FD-SOI wafers, and can quickly expand capacity to meet rising demand.
SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) Last year, the two companies extended their licensing agreement and expanded their technology cooperation.
The specs for FD-SOI wafers are very exacting. As Soitec has pointed out, required silicon uniformity across a full 300mm-diameter wafer corresponds to about 5mm (less than a quarter of an inch) over the distance between Chicago and San Francisco.
Here’s what SEH is saying:
Presentations from the Kyoto FD-SOI workshop – including an excellent short course on FD-SOI design techniques – are now freely available on the SOI Consortium website.
STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.”
Can they do it?
Yes, they can.
Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and love. Although the concept is over a decade old, the current technical development is moving at lightspeed.
When ST ported 28nm bulk to 28nm FD-SOI, they did it soup-to-nuts – including wafer processing – in under six months, with amazing results. At VLSI Kyoto, they reported that starting from a direct porting of a bulk planar CMOS SRAM design, the improvement in read current Iread was up to +50% (@Vdd=1.0V) and +200% (@ Vdd=0.6 V), respectively, compared with the original 28nm Low-Power (LP) CMOS technology.
The laying of the foundation – writing compact and SPICE models – has long been done. As Leti’s Olivier Rozeau explained in his article about Leti’s 28nm FD-SOI Compact models a few years ago in ASN, robust models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to committing a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
And when Mentor moved the Leti models to robust circuit simulators, they did it in under two years. Phenomenal! Leti’s 14nm models are now done, and the PDKs will be ready in Q3’13.
In fact, Leti is now working on models for 10nm FD-SOI, for which they’ll have PDKs in a year. That means all systems are go for 10nm FD-SOI in 2016. (And by the way, Leti CEO Laurent Malier also says that for boosting pFETs with SiGe, they’re seeing better results with FD-SOI than bulk FinFETs.)
What about manufacturing? Fabs typically take about a year to re-characterize their processes for a shrink. Moving from planar 28nm to 14nm FD-SOI is a straight shrink of what is essentially a legacy technology. Again, no showstoppers.
From a manufacturing standpoint, there are no gotchas, no special equipment. As Chery noted in an ASN interview last fall, “On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.”
The ultra-thin wafers have been ready for years, and have multiple sources including Soitec and SEH.
In terms of design, the design flows, methodologies and tools are the same as designers have always used. And, with FD-SOI, biasing efficiency (not possible in FinFETs) is an added bonus. ST has published figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at low power 0.6V – especially good news for anything with a battery.
In fact, Leti’s Malier recently highlighted that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
Leti’s finding that boosters like strain add another 10% to the performance figures: so overall with boosters they’re seeing +40% performance at the same supply voltage (Vdd) moving to 14nm, and another 30% moving to 10nm.
In discussing the two flavors of FD-SOI they have planned, Subi Kengeri, Vice President of Advanced Technology Architecture at GlobalFoundries points to this ST slide regarding timing:
The icing on the cake is the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In particular, the recently announced €360 million FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is a plum. While the European workforce will certainly be the first to benefit from this, it is a strong endorsement of FD-SOI and really good news for the entire FD-SOI ecosystem.
Chery sees big opportunities for FD-SOI. At the ST Technodays (4 June 2013), he told ASN he’s targeting mobile, as well as networking/servers, gaming and apps, including set-top boxes. (And he also hinted that we should be on the look-out for some big announcements.)
So those folks that give bulk FinFETs an edge in the race to 14nm better keep the pedal to the metal and their eyes on the road as FD-SOI has a tuned engine and a smooth track. Buckle your seatbelts: the race is on.
The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).
Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.
These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.
The 28nm FD-SOI technology offer:
Advances in Technology Development:
The organizers for this event are:
BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.
Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).
It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.
SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.
With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.
As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”
SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”
Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.
SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.
With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”
As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”
The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.
The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.
So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.