Tag Archive SemiWiki


FD-SOI Everywhere: GF & Samsung Videos, Press, Conferences and more – a quick roundup

Over the last few weeks there’s been another burst of activity in the FD-SOI arena. A new round of articles, videos and conferences are making FD-SOI the centerpieces. Here’s a quick round-up of things you won’t want to miss.

GlobalFoundries video

Info on GlobalFoundries 22nm FD-SOI offering just keeps on coming. Following the ASN roundup of info from the summer and fall (missed it? read it here), they’ve posted yet another excellent FD-SOI video:GF22_FDSOI_BodyBias_video

How to optimize power and performance with 22FDX™ Platform body-biasing – Dr. Jamie Schaeffer gives a quick (under 3 minute) guide to the basics of front and reverse body-biasing, and the GF approach to a dynamic trade-off between power and performance . He explains how forward body bias (FBB) boosts performance at both high and low voltages, and how reverse body bias (RBB) cuts leakage for the lowest standby power. He also touches on FBB techniques for analog/RF designs.

Samsung video

Samsung28FDSOI_runnersThey’re back! Though they’ve been pretty quiet recently, this latest Samsung video on their 28nm FD-SOI foundry offering hits right at the heart of IoT. Entitled The IoT Revolution and Samsung Foundry’s 28nm FD-SOI, the fun two-minute spot features two runners talking shop during a break. She asks: Is there a lot of design ecosystem support for FD-SOI? He answers: Absolutely. And he goes on to talk about the EDA/IP ecosystem they’re building. It ends on this tantalizing note: He: So you’re done? She: Not! Race you to the next station! He: Oh, it’s on!


With reader interest high and higher, FD-SOI continues to get great coverage in SemiWiki.com. Here are some recent good reads:

IP-SoC Rebound in 2015 ! – IP expert Eric Esteve covers FD-SOI highlights from the upcoming IP-SOC 2015 conference in Grenoble, France (2-3 December 2015), including these presentations (full program here):

  • FDSOI is taking on speed as platform and a European focus project by Gerd Teepe, GlobalFoundries
  • FDSOI IP Shop: The key enabler of success by Patrick Blouet, Collaborative program manager, STMicroelectronics
  • Strategies for SoC / IP Design for Emerging Applications: An Indian perspective by Samir Patel, Sankalp Semiconductor
  • Assessing and managing the IP Sourcing Risk by Philippe Quinio, STMicroelectronics
  • Power Planning and Timing Signoff Solutions by SOI guru and ARM Fellow Jean-Luc Pelloie
  • FD-SOI a New Era for Power Efficiency: Why and How? By Olivier Thomas, Silicon Impulse, CEA – LETI (btw, if you missed his excellent ASN piece explaining Leti’s Silicon Impulse program, you can still read it here)

28nm FD-SOI: A Unique Sweet Spot Poised to Grow – Pawan Fangaria explains why “…today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on.”

Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node – Tom Simon was at ARM Techcon, where he attended a talk sponsored by Cadence on the topic of using GlobalFoundries 22nm FD-SOI process to implement a quad core ARM Cortex-A17. He shares a number of the key slides in this informative blog.


SemiEngineering Editor-in-Chief Ed Sperling continues his great line-up of incisive interviews. In Increasing Challenges At Advanced Nodes, he gets some spot-on FD-SOI quotes from GlobalFoundries CTO Gary Patton, including:

  • “It’s great that you get finFET performance at 28nm cost. But what’s really interesting for me is that you get software control. You can turn chips, blocks and circuits on and off. It’s a whole new degree of freedom for the designer.”
  • “ I believe 22nm FD-SOI fits the sweet spot.”
  • “We wouldn’t do 14nm FD-SOI. We would want a bigger jump than that. It would something closer to 10nm.[…] …it would be planar. If you go to finFET, you would lose the back body biasing. That’s a key attribute.”

ByGianni PRATA

SemiWiki Logs >200,000 Hits on FD-SOI Posts

SemiWiki founder Dan Nenni notes that their 41 FD-SOI related posts to date have drawn over 200,000 views (you can read his whole post about it here). Of that, he notes, over 60,000 came to the site directly via a search for the keyword FD-SOI. “So, if there is a question in your mind as to when FD-SOI will come to the mainstream semiconductor market the answer is very soon, absolutely,” he concludes.

ByGianni PRATA

Semiwiki Reveals TSMC’s FD-SOI Patent Activity

Revelations by semiwiki’s Eric Esteve that TSMC has filed a significant FD-SOI patent has generated a rush of speculation in the press and online forums.  In his piece When TSMC advocates FD-SOI…,  Esteve noted that TSMC’s patent for “Planar compatible FDSOI Design Architecture” (granted 14 May 2013) heralded the advantages as follows: “Devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption.”

In a subsequent article in Electronics Weekly entitled TSMC Developing FD-SOI, David Manners concluded, “Clearly all mobile IC houses are looking at FD-SOI as an option because of its lower power potential. The fact that TSMC is developing the technology suggests that a customer or customers have enquired about using FD-SOI…”.


Good FD-SOI Summer Reading & Viewing


Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher.

But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.

In mid-June, Samsung posted a video of their DAC presentation, Samsung 28nm technology for the next big thing on YouTube.  Presented by JW Hwang, Principal Engineer for Samsung Electronics, it runs almost 14 minutes long, with the entire second half devoted to 28nm FD-SOI.  Here are some key points made therein:

  • The smartphone market is saturating, except in China.
  • Internet of Things (IoT) is The Next Big Thing – and it’s a far bigger market (heading towards $9 trillion per IDC) than smartphones. It’s about affordability & connectivity, with a lot of sensors and generating a lot of data (which will need low-power processing).
  • 28nm is the sweet spot, and FD-SOI simplifies processing, lowering costs – and it gets better performance.
  • Designers shouldn’t be afraid of FD-SOI, as the design flow is the same as bulk planar, and there’s a lot to be gained by body biasing.
  • Most of the IP is already product-proven, and the PDK is currently available.
  • The technology transfer from ST to Samsung is underway, and Samsung expects to have it fully qualified for high volume by March 2015.
  • A second generation with additional IP that will further decrease chip size is also in the works.
 Samsung2814FD  Samsung228FDready

Samsung DAC ’14 video – process complexity vs. performance/power.

Samsung DAC ’14 video – 28nm FD-SOI is  product-proven

Here at ASN, of course, there was the terrific piece by industry expert Handel Jones (IBS) entitled FD-SOI: The Best Enabler for Mobile Growth and Innovation.  IBS concludes the benefits of FD-SOI are overwhelming for mobile through Q4/2017. Jones also looks for it to have a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs.

Also in ASN, we covered the SOI Papers at the 2014 VLSI Symposia.   Three top SOI-based papers included one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs, and the two on 10nm SOI FinFETS. (In Part 2, we covered the rest of the SOI papers.)

Elsewhere, we saw high-profile, open debate, which is excellent and necessary.  Semiwiki has been a great platform for discussion, with a steady flow of FD-SOI articles – many of which generate ferociously active discussions in the comments section. Here’s a round-up of what went on this summer:

  • Is SOI Really Less Expensive? by Scotten Jones (24 June ’14) generated a whopping 56 comments.  Jones’ company, IC Knowledge, used its IC cost modeling on bulk planar, FD-SOI, bulk FinFETs and SOI FinFETs. Jones concluded that at 14nm, costs were fairly comparable, which was hotly debated by readers (with FD-SOI supporters fortifying their claim that it comes in significantly cheaper). However, no one quibbled with Jones’ final conclusion: “Decisions on which process to pursue are therefore expected to be driven by factors other than cost.”
  • Keywords: FD-SOI, Cost, FinFET by Eric Esteve (15 July ’14) followed up on Jones’ piece, generating another super-heated round of comments: 41 in all. Esteve dove into the different approaches to multiple threshold voltages (Vt) between FD-SOI and FinFET, and looked at the advantages of biasing in FD-SOI, concluding that FD-SOI should do 10% better on cost than Jones projected. Heavy hitters from all sides chimed in, many with very insightful and sometimes deeply technical information and explanations.
  • Setting the Record Straight on FD-SOI Costs by Scotten Jones (21 July 14) pushed back on the Esteve “keyword” piece, as well as on an ASN blog, “Is FD-SOI Cheaper? Why yes!”, (27 June ’14).  However, in the end, he reminded readers that costs won’t be the deciding factor.
  • FD-SOI: 20nm Performance at 28nm Cost by Paul McLellan (28 July ’14) covered a presentation given by Samsung’s Kelvin Lo about their foundry strategy at the CSPA (Chinese Semiconductor Professionals Association) meeting. Low reiterated that 28nm FD-SOI is the sweet spot for low-power, high performance. McLellan then briefly covered the Cadence quarterly conference call, which indicated interest in FD-SOI is up.
  • FD-SOI Target Applications Are… by Eric Esteve (1 Aug. ’14) looked at the big picture. He had listened to the July ST analyst call, where they said they had 18 FD-SOI ASIC design wins.
  • FD-SOI at 14nm by Paul McLellan (17 Aug. ’14) looks at an ST presentation given at SemiconWest in 2013 – a good overview with some pertinent technical detail.

Next, check out this interesting post in SemiconductorEngineering by Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys.  She gives a very informative perspective on “Power Reduction Techniques” (7 Aug. ’14) in bulk planar, FD-SOI and FinFETs. She talks about how biasing in FD-SOI is highly effective, then goes on to summarize various power-reduction techniques by process node. There’s an excellent summary in her graphic (her Figure 2):


There’s also a terrific chart in the same article based on the annual Synopsys’ Global User Survey (GUS), indicating which power techniques are used most in which applications (mobile, automotive, networking, etc.).

If talk on LinkedIn is any indication, the design community in India is very interested in FD-SOI.  EE Herald published a much-shared interview with ST’s CAD/design solutions director in India (18 July ’14), entitled  FDSOI; The only semiconductor tech to continue Moore’s Law down to 10nm. It gives an excellent overview of the technology, answering some of the basic questions designers are asking.

Finally, the folks at the silicon prototyping brokerage CMP pointed us at a bit of humor – and as they say, a picture’s worth a thousand words….




ByGianni PRATA

FD-SOI Tops 100K SemiWiki Hits

100K views and counting: FD-SOI-related posts on SemiWiki are fabulously popular. Following a wrap-up by Paul McLellen of his FD-SOI talk at EDPS (read post here), heated discussion ensued in the comments section.  To show just how hot a topic FD-SOI is in the design community, SemiWiki co-founder Dan Nenni shared the following stats:

  • 100,000 FD-SOI article views on SemiWiki
  • Top referring domain is intel.com
  • Top geographic regions are North America, Taiwan, Korea
  • 160 FD-SOI blog comments
  • Top Google searches: FD-SOI Wiki, FD-SOI vs FinFET

Clearly, FD-SOI is a hot topic!

ByGianni PRATA

SemiWiki: FD-SOI’s the Technology to Continue Moore’s Law

A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice.  He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog.  A highly recommended read.