If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.
The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.
One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.
This year, papers in the following areas have been solicited:
Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.
EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.
And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).
Grenoble the first week of April 2019 is clearly the place to be.
Three of the world’s More-than-Moore and SOI technology development powerhouses have signed a comprehensive agreement for ongoing collaboration and cooperation in developing new technologies for the emerging IoT market. SITRI of Shanghai, and CEA-Leti and Minatec of Grenoble will work together to accelerate the adoption of their latest technologies and create a global innovation ecosystem for emerging IoT applications (read the press release here).
The framework agreement broadly covers all joint areas of research at SITRI and Leti, including MEMS and sensors, 5G RF front ends, ultra-low power computing and communication, RF-SOI and FD-SOI.
In fact, the trio cites SOI as a key technology in the development of both Moore’s Law and “More than Moore” solutions for the IC industry, as it brings cost, performance, power and integration advantages to the areas of ICs, RF, MEMS, and communications.
“We are confident that this collaboration will be positive for China’s electronics industry, as well as for the Grenoble region’s growing SOI technology ecosystem,” said MINATEC Director Jean-Charles Guibert.
Adds Marie-Noëlle Semeria, CEO of Leti, “Through this partnership, SITRI, MINATEC, CEA-Leti and the entire ecosystem will be able to promote and extend this ecosystem to SOI partners worldwide, and provide SOI solutions to the emerging Chinese IoT market.”
“MINATEC is a world-class international innovation center that fosters a wide range of leading-edge IoT technology research and development which is home to CEA-Leti, the renowned international research institute in microelectronics,” said Charles Yang, President of SITRI. “Through this agreement and SITRI’s established platform for ‘More than Moore’ commercialization, we can accelerate the adoption of these latest technologies and create a global innovation ecosystem for emerging IoT applications.”
Don’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.
As of this writing, the following keynote speakers have been confirmed:
Invited speakers include:
As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.
Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :
For current information on the conference visit the S3S website at: http://s3sconference.org/
LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.
In what may be a first for the MEMS industry, CEA-Leti has manufactured micro-accelerometers on 300mm wafers, a development that could lead to significantly lower MEMS manufacturing costs. And yes, those 300mm wafers are SOI wafers. These are “thick” SOI wafers, with an insulating BOx (buried oxide) layer of 2µm, and top silicon of 220nm.
The most advanced of Leti’s platforms is its M&NEMS technology based on detection by piezo-resistive silicon nanowires, which reduce sensor size and improve performances of multi-axis sensors. Leti’s inertial-sensor manufacturing concept enables the design and fabrication of combo sensors, such as three-axis accelerometers, three-axis gyroscopes and three-axis magnetometers on the same chip. This is a key component for IoT apps.
Leti’s M&NEMS concept, developed with 200mm technology, is currently being transferred to an industrial partner. Demonstration of this technology on 300mm wafers has shown very promising results.
In addition to lowering costs, manufacturing MEMS with 300mm technology enables 3D integration using MEMS CMOS processes in more advanced nodes than on 200mm, and the use of 3D through-silicon-vias (TSV), which is already available in 300mm technology. (Read the full Leti press release here.)
Shanghai-based Simgui has produced the company’s first 200mm SOI wafers based on Soitec‘s Smart CutTM manufacturing technology (read the press release here). Samples will be going to customers in the coming weeks for qualification, with high-volume ramp planned for early 2016. Simgui will be selling the wafers directly to its own customers in China, and manufacturing on an OEM basis for Soitec customers worldwide. This includes manufacturing Soitec’s fabulously successful RFeSI90 substrates for LTE-A, 5G and Gigabit Wi-Fi in smartphones and other devices (read about those here), substantially increasing worldwide capacity to meet the recent rapid rise in demand.
While overall worldwide 200mm wafer demand (including bulk and epi) has slipped a bit over the last year (they’re now accounting for a little over a quarter of all wafer sales), demand is increasing for certain types of 200mm SOI wafers. What’s driving it? RF and smart power (both of which are seeing big opps in automotive). SOI wafer leader Soitec, for example, is seeing an uptick of 20% in 200mm SOI wafers for smart power for automotive. RF is growing even faster.
The thick and thin of it
What’s different about these 200mm SOI wafers? It’s a question of layer thickness, quality and the manufacturing technology used to make them. Simgui and many others have been producing very “thick” 200mm SOI wafers for years. Traditionally in “thick” SOI (which has been used in things like power, aerospace, automotive, MEMS and sensors for decades), the top silicon might be up to anywhere from 2 µm to 300 µm thick, with an insulating box layer in the range of 3 µm (sometimes much more). But new apps in smart power and RF, for example, need a very high quality top silicon layer that might be as thin as 0.145µm for power*, or under 0.1µm for RF. The insulating layer also needs to be far thinner, and the bottom supporting layer also has to fulfill specific, advanced parameters.
(Bear in mind that these wafers for RF and smart power are still relatively thick compared to what you need for FD-SOI, for example, which is considered “ultra-thin”, and has ultra-uniform top silicon with a thickness in the range of 10-20 nm (0.01 – 0.02µm).)
There are several different manufacturing approaches to fabricating SOI wafers. To make the SOI wafers needed for new markets in smart power and RF, Simgui has opted to use Soitec’s Smart Cut technology (which is well-explained here). Smart Cut’s especially good for producing very high-quality wafers, with a thin and very uniform top layer of silicon and a thin layer of insulating buried oxide (BOx).
The new deal
Simgui is a high-tech company in Shanghai focused on supplying SOI wafers and providing foundry services for epi wafers. It was spun off from the Shanghai Institute of Microsystem and Information Technology (SIMIT) within the Chinese Academy of Sciences (CAS) and now is a joint venture with a group of investors from Silicon Valley. Both its SOI and epi businesses are growing dramatically.
With a surge in demand for leading-edge thick 200mm SOI wafers, Simgui partnered with Soitec, the industry’s SOI wafer leader, back in May 2014 (see that press release here).
The May 2014 deal was a licensing and technology transfer agreement under which Simgui would manufacture Soitec’s 200-mm SOI wafers using Soitec’s proprietary Smart Cut™ technology. The news now is that it’s actually happened. Simgui has established a high-volume SOI manufacturing line to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide in the growing RF and power markets. Beyond this initial cooperation, the two companies are expanding their collaborative efforts in the future to take advantage of their synergies.
China markets and beyond
Roughly a third of the fabs in China are 200mm (see SEMI’s map below). As recently noted by IC Insights, “Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.”
The Soitec-Simgui partnership addresses two key areas: 1. China’s growing demand and 2. the need for an increase in worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. It’s also seen as a key element in establishing an SOI ecosystem in China.
Dr. Xi Wang, chairman of the board of directors of Simgui, notes that, “China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry.”
It’s also good news for Soitec’s 200mm SOI customers. “We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.
Which explains why the two companies see it as a win-win situation.
Silicon Europe (an alliance of Europe’s leading micro- and nanoelectronics clusters) and the SOI Consortium have organized an SOI Workshop on the 7th of July 2015, during the 10th Silicon Saxony Day in Dresden.
Here’s the agenda:
The workshop, which runs from 1:30 – 4:30, will be held in English. There is an entry fee (waived for students) for Silicon Saxony Day, but once you’re in, the SOI Workshop is free.
With five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.
Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?
Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.
Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.
ASN: When did X-Fab first start offering SOI and why?
TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.
ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?
TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.
Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.
ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?
TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.
Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.
ASN: When and why do your customers choose an SOI-based process?
TM: Typically, we see two types of SOI customers:
ASN: Can you expand on the time-to-market (TTM) issue a bit?
TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.
ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?
TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.
ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?
TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..
ASN: Can you tell us more about X-Fab’s SOI offerings?
TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)
Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.
XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.
XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.
ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?
TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.
For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.
We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.
ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?
TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.
We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.
We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.
ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?
TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.
~ ~ ~
X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.
~ ~ ~ ~
* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge
**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.
CEA-Leti, a leading global center for applied research in microelectronics, nanotechnologies and integrated systems, is proudly hosting its 17th LetiDays in Grenoble on June 24–25, 2015, and associated seminars and workshops on June 22nd, 23rd and 26th (click here to go to the registration site).
On June 22-23, Leti will present their first workshop on FD-SOI. This Forum brings together a stellar line-up from academia, semiconductor companies, system design houses and the EDA industry to build a vision of the strategic directions and state-of-the-art in FDSOI IC design. Click here to see the schedule – it’s impressive.
The big themes for this year’s Leti Days are Internet of Things-augmented mobility, and managing connected devices and the services and apps they offer. This also gives Leti a chance to show off their remarkable array of technological breakthroughs in silicon technologies, sensors, telecommunications, power management in wearable systems, health applications, the transport market up to the factory and cities of the future.
The event will feature 40+ conferences, many networking opportunities, a showroom and exhibition halls. You’ll hear and meet market leaders, startups, analysts and Leti technology experts. As with every Leti Days event, you’ll get a comprehensive vision of the latest innovations in key technologies and markets, and be provided with opportunities to complement your roadmaps with Leti expertise.
If you can’t make it to Grenoble, watch for other Leti Days coming up in San Francisco during Semicon West and in Tokyo, among others.
International research teams working on or interested in the far-reaching SOIPIX radiation-detector project have a workshop coming up in June. The project was originally started by KEK* scientists to develop a new detector technology and quantum beam imaging for high-energy particle physics. As research teams around the world (including Japan, USA, China and Europe) joined to take advantage of the multi-wafer project runs, it soon expanded to include more applications. (To learn more about the program, click here.)
Leveraging the SOIPIX strategy of SOI-based monolithic sensor-electronics integration, applications are now being developed in areas such as medical (x-ray sensors and radiotherapeutic systems), materials research, nuclear physics, astrophysics, electron microscopy and industrial uses (such as x-ray inspection systems).
(Here at ASN, we covered the project and its implications for medical imaging back in 2010 – click here to read that piece.)
The next workshop, SOIPIX2015, will take place at Tohoku University (Sendai, Japan) 3-5 June 2015. Registration has been extended until 22 May 2015. Click here for registration information.
*KEK is Japan’s High Energy Accelerator Research Organization.
ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.
Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?
Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.
ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?
ASN: At what point in the design process do you typically come in? What sorts of services do you offer?
SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.
ASN: What do you see as the advantages of FD-SOI?
SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.
We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.
ASN: Designers of what kinds of chips should be thinking about FD-SOI?
SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.
ASN: Why do they ultimately choose it? Why do they hesitate?
SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.
ASN: Are there special considerations designers should think about before starting a project in FD-SOI?
SB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.
ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?
SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.
Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.
ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?
SB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market
ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?
SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.
ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?
SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.
We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.
~ ~ ~
Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.