Tag Archive silicon-on-insulator

VLSI Research names Soitec CEO to 2015 All Stars of the Semiconductor Industry

Paul Boudre has been named CEO of Soitec.

Soitec CEO Paul Boudre

VLSI Research Chip Insider has named Soitec CEO Paul Boudre to its roster of 2015 All Stars of the Semiconductor Industry. (See the announcement here.)Soitec

Boudre was cited for “…successfully re-organizing Soitec back to its core business as a leading innovative engineered substrate supplier. His first year results are already astounding, with very high growth rates.” Getting FD-SOI and RF-SOI into the mainstream figured among the notable accomplishments that elevated him to these ranks.

Congratulations to Paul Boudre and the entire Soitec team for this important recognition by one of the industry’s leading analyst groups.

Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

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Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

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Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

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Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

Interview: Leti Is the Moving Force Behind FD-SOI. CEO Marie Semeria Explains the Strategy (part 1 of 2)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

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Marie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

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Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

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Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

Click here to read part 2 of this exclusive interview.

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.

First SOI wafers based on Smart Cut tech produced in China, target strong 200mm SOI demand in smart power, RF, automotive

Shanghai-based Simgui has produced the company’s first 200mm SOI wafers based on Soitec‘s Smart CutTM manufacturing technology (read the press release here). Samples will be going to customers in the coming weeks for qualification, with high-volume ramp planned for early 2016. Simgui will be selling the wafers directly to its own customers in China, and manufacturing on an OEM basis for Soitec customers worldwide. This includes manufacturing Soitec’s fabulously successful RFeSI90 substrates for LTE-A, 5G and Gigabit Wi-Fi in smartphones and other devices (read about those here), substantially increasing worldwide capacity to meet the recent rapid rise in demand.

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Simgui’s first 200mm SOI wafer manufactured using Soitec’s Smart Cut technology. (Courtesy: Simgui)

While overall worldwide 200mm wafer demand (including bulk and epi) has slipped a bit over the last year (they’re now accounting for a little over a quarter of all wafer sales), demand is increasing for certain types of 200mm SOI wafers. What’s driving it? RF and smart power (both of which are seeing big opps in automotive). SOI wafer leader Soitec, for example, is seeing an uptick of 20% in 200mm SOI wafers for smart power for automotive. RF is growing even faster.

The thick and thin of it

What’s different about these 200mm SOI wafers? It’s a question of layer thickness, quality and the manufacturing technology used to make them. Simgui and many others have been producing very “thick” 200mm SOI wafers for years. Traditionally in “thick” SOI (which has been used in things like power, aerospace, automotive, MEMS and sensors for decades), the top silicon might be up to anywhere from 2 µm to 300 µm thick, with an insulating box layer in the range of 3 µm (sometimes much more). But new apps in smart power and RF, for example, need a very high quality top silicon layer that might be as thin as 0.145µm for power*, or under 0.1µm for RF. The insulating layer also needs to be far thinner, and the bottom supporting layer also has to fulfill specific, advanced parameters.

(Bear in mind that these wafers for RF and smart power are still relatively thick compared to what you need for FD-SOI, for example, which is considered “ultra-thin”, and has ultra-uniform top silicon with a thickness in the range of 10-20 nm (0.01 – 0.02µm).)

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This graphic explains which SOI wafers are used for which applications, correlating top silicon and insulating buried oxide layer thicknesses.

There are several different manufacturing approaches to fabricating SOI wafers. To make the SOI wafers needed for new markets in smart power and RF, Simgui has opted to use Soitec’s Smart Cut technology (which is well-explained here). Smart Cut’s especially good for producing very high-quality wafers, with a thin and very uniform top layer of silicon and a thin layer of insulating buried oxide (BOx).

The new deal

Simgui is a high-tech company in Shanghai focused on supplying SOI wafers and providing foundry services for epi wafers. It was spun off from the Shanghai Institute of Microsystem and Information Technology (SIMIT) within the Chinese Academy of Sciences (CAS) and now is a joint venture with a group of investors from Silicon Valley. Both its SOI and epi businesses are growing dramatically.

With a surge in demand for leading-edge thick 200mm SOI wafers, Simgui partnered with Soitec, the industry’s SOI wafer leader, back in May 2014 (see that press release here).

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Simgui’s Fab-3 in Shanghai, where the company is manufacturing 200mm SOI wafers for power & RF using Soitec’s Smart Cut technology.

The May 2014 deal was a licensing and technology transfer agreement under which Simgui would manufacture Soitec’s 200-mm SOI wafers using Soitec’s proprietary Smart Cut™ technology. The news now is that it’s actually happened. Simgui has established a high-volume SOI manufacturing line to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide in the growing RF and power markets. Beyond this initial cooperation, the two companies are expanding their collaborative efforts in the future to take advantage of their synergies.

China markets and beyond

Roughly a third of the fabs in China are 200mm (see SEMI’s map below). As recently noted by IC Insights, “Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.”

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Current map of fabs by wafer diameter in China (as of April, 2015, Courtesy: SEMI)

The Soitec-Simgui partnership addresses two key areas: 1. China’s growing demand and 2. the need for an increase in worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. It’s also seen as a key element in establishing an SOI ecosystem in China.

Dr. Xi Wang, chairman of the board of directors of Simgui, notes that, “China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry.”

It’s also good news for Soitec’s 200mm SOI customers. “We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.

Which explains why the two companies see it as a win-win situation.

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

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Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

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The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

Go! FD-SOI Wafer Suppliers Ready for High-Volume Ramp; Atomic-Scale Uniformity Assured

With the great news about FD-SOI foundry offerings from Samsung, ST and now GlobalFoundries, plus the IP availability, the wafer suppliers have chimed in to remind the ecosystem they’re ready to ramp (and have been for a number of years!). So the wafers are ready (and they truly are amazing), the processes ensuring high yield are in place, and high-volume capacity is ready to roll. Most recently in the wafer news, top-10 equipment supplier Screen Semi Solutions has joined the ecosystem (press release here) with wafer cleaning processes that ensure and maintain the requisite wafer uniformity in high-volume FD-SOI wafer production.

The industry-standard process for making all the different flavors of silicon-on-insulator (SOI) wafers (FD-SOI, RF-SOI, power, photonics, etc.) is Soitec’s Smart CutTM technology (you can learn about how it works here). Invented at Leti and industrialized by Soitec, Smart Cut made its world debut at Semicon West 20 years ago (!!) in 1995.

But for FD-SOI, the SOI wafers needed to meet new exigencies of extremely thin and uniform top silicon and an extremely thin insulating (aka Buried Oxide, or BOx) layer. Consider this: uniformity of the top silicon layer of Soitec FD-2D wafers (that’s the wafer product name) is guaranteed to within +/-5Å at all points on all wafers. This uniformity is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. Meeting this requirement is not new: Soitec announced they were ready for industrialization with this level of uniformity back in 2010.

As ST’s godfather of FD-SOI, Thomas Skotnicki, noted at Leti Days in Grenoble a few weeks, Soitec made even greater strides in the wafer requirements for the 14nm node. The FD-SOI offering just announced by GF is referred to as 22nm, but that really means a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end.

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The Alps tower behind Soitec’s SOI wafer manufacturing facility near Grenoble, France. (Photo credit: A. Hars)

Here’s what Paul Boudre, CEO of Soitec had to say about the GF announcement: “GlobalFoundries’ announcement is a key milestone for enabling the next generation of low-power electronics and we are very pleased to be GlobalFoundries’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology. With our two fabs and our worldwide licensing strategy, the market will enjoy all of the SOI wafers it needs for strong adoption. The markets we are addressing with this product will be key contributors to Soitec’s growth.”

For a number of years now, Shin‐Etsu Handotai (SEH), the world’s largest maker of silicon wafers, has been saying that they’re meeting the specs for FD-SOI wafers, too (read about that here), and can quickly expand capacity to meet rising demand. SEH is a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers. They’ve been making SOI wafers since 1988, and in 1997 first introduced SOI wafers produced using Soitec’s Smart Cut technology. (And of course Soitec and SEH continue their long-standing collaboration – read about that here.)

So with the GF announcement, Nobuhiko Noto, general manager of SOI Division at SEH, said, “SEH welcomes this development, bringing FD-SOI products to the industry, and we look forward to the continuation of our work in extending the global supply chain for FD-SOI. We are very glad to be engaged in supporting the growth and development of the FD-SOI market, own FD-SOI wafer supply.”

So no worries about wafer supply. As Dr. Handel Jones, CEO of IBS notes, “Multi-source supply chain for substrates has been established, and wafer volumes can potentially be one million per year and more in the future. We are confident that Soitec and its licensing to supply the substrates required to allow FD-SOI wafer volumes to reach their potential.” (You can read Dr. Jones’ ASN posts here.)

Maximizing production yields with atomic-scale uniformity

At Semicon West, Soitec and Screen Semiconductor Solutions announced they have jointly developed a process to ensure atomic-scale uniformity of ±5 angstroms across the surface of all 300-mm FD-SOI wafers at the high-volumes the industry needs.

Maximizing FD-SOI production yields is of course critical to meeting worldwide market demand.

“Our strategic partnership with Screen enables us to produce ultra-thin FD-SOI substrates that meet chip makers’ challenging requirements of atomic level resolution in high volume manufacturing. Our FD-SOI wafers are already qualified by a number of foundries,” said Christophe Maleville, senior vice president of Soitec’s Digital Electronics Business Unit. “We are extremely pleased to see such high support from Screen on FD-SOI manufacturing and we are looking forward to finalize our on-going efforts on 14nm FD-SOI node.”

“Screen is proud to collaborate with Soitec on meeting this advanced technical challenge and enabling FD-SOI technology to reach high performance levels,” said Screen CTO Dr. Olivier Vatel.“Our high-productivity cleaning systems are available and ready for the FD-SOI ecosystem. As an industry leader, we will continue to deliver world-class products that contribute to our customers’ market success.”

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The Screen Semiconductor Solutions Single Wafer Cleaner SU-3200 is used by Soitec for high-volume FD-SOI wafer manufacturing (Picture courtesy: Screen Semi)

Screen’s single-wafer cleaning equipment, the SU-3200, delivers the industry’s best productivity by using a perfect balance of high-speed cleaning capacity and highly stable processing. It has multiple process chambers, allowing each wafer to be treated individually with its own dedicated recipe based on incoming layer thicknesses, the desired surface condition to be achieved and a predictive etch model. Key advantages of the system include highly uniform chamber-to-chamber processing and cycle times for robust results, tight control of layer thicknesses, the elimination of defects and metal contamination and high productivity enabled by a versatile chemical-supply system.

So it’s all systems GO!

Soitec Appoints New CFO

SOI-wafer leader Soitec has appointed Grégoire Duban as Chief Financial Officer. This recruitment supports the ongoing strategic refocusing of the Group’s activities on its core electronics business, as Soitec announced on January 19 (read full press release here). Duban will report directly to Soitec CEO Paul Boudre.

“Grégoire Duban possesses over 18 years’ experience in leading change under corporate restructuring programs at groups in the energy, digital and automotive sectors. His expertise is focused on improving operating performance, implementing new business models, restructuring operations and refocusing businesses to increase the profitability of groups in transition, such as ours. I am delighted to welcome him on board”, says Boudre.

He adds, “I would also like to express my gratitude to Olivier Brice, who is leaving his position as Chief Financial Officer to move on to new responsibilities, after supporting Soitec in recent years with tremendous professionalism and outstanding commitment.”

X-Fab Interview: SOI Solutions for analog/mixed-signal, high-voltage, high-temperature and MEMS Applications

X-FAB_logo_print_loresWith five manufacturing sites around the world and 72,000 wafer starts/month, X-Fab is a leading pure-play analog/mixed-signal and specialty foundry for automotive, industrial and medical applications. ASN recently had the opportunity to talk to Tilman Metzger, Product Marketing Manager for the X-Fab Group, about when customers choose an SOI-based offering.

Advanced Substrate News (ASN): Can you give us an overview of the SOI offering at X-Fab?

Tilman Metzger (TM): X-FAB offers a range of SOI solutions from 1µm to 0.18µm. We support high voltage (HV) requirements from 20V to 650V. X-FAB also targets very high temperature applications of up to 225˚C.

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Tilman Metzger, Product Marketing Manager for the X-Fab Group. (Courtesy: X-FAB)

Our latest addition to the SOI family is XT018, our first 0.18µm SOI solution. The modular XT018 platform combines a state-of-the-art 180nm mixed-signal process with benefits of a robust SOI HV technology. XT018 supports voltages up to 200V and targets next generation automotive and industrial applications.

ASN: When did X-Fab first start offering SOI and why?

TM: We started more than 15 years ago with a 2µm HV SOI process. Our first SOI development was driven by specific customer requirements for an HV motor driver application.

ASN: What sorts of chips are currently being manufactured by X-Fab using SOI?

TM: X-FAB solely focuses on analog and high-voltage SOI applications. We do not target RF-SOI or high density SOCs like CPUs etc.

Typical products include high-side gate pre-driver ICs, motor driver ICs, ultrasound driver ICs, solid state relays, optocoupler and analog switch arrays.

ASN: For X-Fab, what are the traditional SOI markets (both in terms of end-markets and geography)? How do you see it evolving?

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X-FAB headquarters in Erfurt, Germany (Courtesy: X-FAB)

TM: Historically, we have seen demand for SOI-based technologies mainly from the industrial sector. That said, we expect to see more automotive customers adopt our SOI solutions in the future.

Geographically, our SOI customer base mostly originates from North America, Europe and Japan. Customers from Greater China and South Korea are generally slower in adoption but gaining momentum.

ASN: When and why do your customers choose an SOI-based process?

TM: Typically, we see two types of SOI customers:

  1. Those that tried and failed a particular design in a BCD/Bulk technology and hence turned to a SOI solution; and
  2. Those that focus on SOI technology right from the start due to IC or system requirements (or past experience). Some of the challenges of such designs may include:
  • Very high temperature of 175-225°C
  • Resistance to EMI* or stringent EMC and ESD requirements
  • Latch-up concerns
  • Negative voltage swings / inductive loads
  • Stringent noise immunity / cross-talk requirements
  • Low leakage at high temperature
  • Aggressive time-to-market requirements

ASN: Can you expand on the time-to-market (TTM) issue a bit?

TM: Since SOI substrates are more expensive than normal bulk wafers, the average wafer price is also higher. Typically customers look at a straight cost-per-die calculation when evaluating the business case for their product. But there’s also the aspect related to ease of design – with SOI, design is easier, so the design cycle might be faster and less costly in terms of engineering time. As a result, if customers can launch their product faster, they can grab more market share and increase their profits.

ASN: What kind of support do you offer designers for SOI-based chips? Is it different from the sort of support for bulk processes?

TM: Generally, for our SOI technologies we offer the same comprehensive support as for our bulk solutions. In addition, we provide SOI application notes that discuss SOI related design considerations. With the exception of XI10, the SOI material we are using is “thick film” SOI, where the device layer is up to 55µm thick, so the behavior of active devices is similar to those on non-SOI substrate. Let’s consider the designers doing high-voltage analog: in bulk, they do standard junction isolation, but in SOI they use deep trench isolation, which actually comes with fewer parasitics, so it’s easier to simulate and design.

ASN: Would you say the SOI ecosystem is well established in the markets X-Fab serves?

TM: There are no special SOI ecosystem requirements for X-FAB’s SOI solution. We use established SOI wafer suppliers and support all major EDA platforms (Cadence, Mentor, Synopsys, Tanner). with complete design kits. Analog and high voltage is all about customization. In the analog world, there are some generic IPs, but most of it is specialized. We offer basic IPs for SOI solutions including I/O and standard cell libraries and memories such as OTP, SRAM etc. which is similar to our offering for non-SOI processes..

ASN: Can you tell us more about X-Fab’s SOI offerings?

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X-FAB cleanroom in Kuching, Malaysia, where the company runs their new XT018 SOI process. (Courtesy: X-FAB)

TM: X-Fab has two one-micron SOI ultra-high-voltage process offerings for 650 Volt and 350 Volt which are used by customers for applications that plug directly into the grid. There is also a big market for 600V IGBT and MOSFET driver ICs. Some customers select these processes for their inherent robustness in applications like avionics and aerospace. (We do not offer specific radiation-hardened solutions, but our customers use these when they have particular reliability requirements.)

Our one-micron process XI10 targets very high-temperature applications: it offers different metallization schemes, and can support up to 225°C.

XT06 is a 0.6µm SOI technology that supports voltages up 60V and is popular across a range of industrial applications.

XT018 is our latest SOI solution. As mentioned earlier it not only targets industrial and medical applications, but also next generation automotive products. An example is the new CAN FD** standard which is more complex and challenging to implement. XT018 offers the right process options to address these requirements. X-FAB has a long successful track record of serving the automotive market. This is also reflected by the fact that the automotive segment accounts for more that 50 percent of our total revenue.

ASN: For MEMS, when and why do your customers opt for an SOI-based solution? Do you see any growth in interest in putting MEMS on SOI?

MEMSfoundryaward_Xfab

X-FAB MEMS Foundry received the “MEMS Foundry of the Year” award at the Best in MEMS & Sensors Innovation Awards ceremony, as part of the MEMS Industry Group’s 10th annual MEMS Executive Congress® held in Scottsdale, Arizona in November 2014. (Courtesy: X-FAB)

TM: For MEMS, we definitely see the opportunity to take advantage of SOI material. In general, SOI wafers are interesting for the formation of highly uniform silicon membranes or other mechanical structures, especially if we prefer to use SOI’s mono-crystalline properties rather than depositing poly silicon. The top device layer is ideal for defining silicon features with thicknesses from a few microns to several tens of microns, without the effort of very long silicon deposition times. The buried oxide (BOX) layer acts as a natural etch-stop layer during silicon etching, at the etching either from the front or from the back of the wafer. Stopping at the BOX layer mitigates any non-uniformity for the deep silicon etch and allows for great process control.  

For instance, at X-FAB, we use SOI wafers to manufacture our open-platform gyro sensor / accelerometer process. We use the SOI wafer’s device layer to make single-crystal masses with uniform thickness for predictable and robust performance. In this case the buried oxide layer not only acts as an etch stop when etching the silicon but is also a sacrificial material to remove from underneath silicon structures such as inertial masses and comb-drives.

We also have our newer three-axis gyro / accelerometer process where X-FAB is making its own SOI substrate with buried cavities. In other cases, we etch a pattern all the way through the back side of the wafer to leave thin membranes on the front side of the wafer. Again, the etch is well-controlled, stopping on the buried oxide and the remaining oxide / device layer silicon membrane could be used on its own or with further layers and structuring to form a variety of device types such as pressure sensors, force sensors, thermopile structures or microphones.

ASN: Do you see SOI becoming a more important part of X-Fab’s offering? If so, why?

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Chips manufactured by X-FAB go into key automotive systems. (Courtesy: X-FAB)

TM: Yes. One of the factors that we foresee to drive SOI based designs is the increasing challenges of automotive systems and ICs. This is largely driven by newer standards like CAN FD. While SOI is is still a relatively small part of our business, we see opportunities, especially with our XTO18 offering, which may open new high-volume markets.

We have customers that require a stable supply of their product over a long period in time, often for a decade or more. In the automotive industry, those customers are using a 10-year old process. We need to be able to guarantee that those processes will be available for ten to fifteen years.

We have customers in consumer markets using SOI – either because they’ve tried and failed on bulk, or they’re looking for long-term solutions. They see the benefits in the ease and speed of design, which helps them ensure that they don’t miss windows of opportunity. But they need to crunch the numbers themselves. SOI will give them a smaller chip size, but there is not a “one fits all” approach – it depends on the design topology.

ASN: Will the SOI-based processes offered by X-Fab evolve? If so, how and why?

TM: Remember, analog and mixed-signal is not a linear shrink like for digital. The node at 0.18 microns is the leading edge for high-voltage. We can add more functionality and more voltage classes. We’ll continue to add features and modules where we see opportunities for increased performance or new markets. That said, for the five platforms in our current SOI offering, the mature ones won’t change too much except for increasing performance. The markets are evolving, but they’re also very conservative.

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X-Fab has organized a series of design webinars, including a number that cover SOI-related topics. Click here to access the list.

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* EMI = electromagnetic interference; EMC = electromagnetic compatibility; ESD = electromagnetic discharge

**CAN stands for controller area network, a protocol that allow microcontrollers and other devices to communicate without a CPU. It is used extensively in automotives for connecting electronic control units (ECUs) and in industry for factory automation. CAN FD is CAN with Flexible Data rates.

IBM Photonics (That’s SOI!) Ready for Cloud, Big Data Apps

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Cassette carrying several hundred chips intended for 100 Gb/s transceivers, diced from wafers fabricated with IBM SOI-CMOS Integrated Nano-Photonics Technology. The dense monolithic integration of optical and electrical circuits and the scalable manufacturing process provide a cost-effective silicon photonics interconnect solution, suitable for deployment in cloud servers, datacenters, and supercomputers. (US quarter coin shown for scale.) (Courtesy: IBM)

For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which the company says will soon enable manufacturing of 100 Gb/s optical transceivers (read the press release here). This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.

Early in the program (back in 2007), IBM contributed a piece to ASN about why their photonics program is on SOI – you can read that here. (Most all photonics — except the lasers — are on SOI. You can read more ASN photonics pieces from Intel and others here.)

Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.

IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.

IBM presented details at the recent 2015 Conference on Lasers and Electro Optics.