Tag Archive silicon-on-insulator

ByAdministrator

Design Highlights: ST-Ericsson’s 28nm FD-SOI SmartPhone/Tablet Chip

Just Posted: FD-SOI video & white paper. Just as this blog was going online, ST-Ericsson posted an excellent, in-depth white paper; and in partnership with STMicroelectroics, a YouTube video detailing the how’s and why’s of FD-SOI.Here are the links — you really don’t want to miss these:

Multiprocessing in Mobile Platforms: the Marketing and the Reality
In this white paper, ST-Ericsson’s Marco Cornero and Andreas Anyuru “…illustrate and compare the main technological options available in multiprocessing for mobile platforms, highlighting the synergies between multiprocessing and the disruptive FD-SOI silicon technology used in the upcoming ST-Ericsson products.”

An Introduction to FD-SOI
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STMicroelectronics and ST-Ericsson have teamed up on this excellent video, which garnered 1250 views within the first four days of its posting on YouTube. The animations and comparisons highlight why FD-SOI is so fast, and so cool. If you have a Google or YouTube account yourself, you can hit the “Like” button.

In the last blog, we kicked off what promises to be an exciting year with the news that ST-Ericsson announced the NovaThor™ L8580 ModAp.  It’s billed as “the world’s fastest and lowest-power integrated LTE smartphone platform,” is built on STMicroelectronics’ 28nm FD-SOI, and is sampling in Q1 2013.

We said it was a game changer, and ST-E’s put together a really good page on their website that shows how they’re doing it.

By way of reminder, the NovaThor L8580 integrates an eQuad 2.5GHz processor (the mobile industry’s fastest) based on an ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

The ST-E site is well worth looking at yourself – but in the meantime, here are a few of the highlights they’re sharing:

  • With FD-SOI, you can do much more with body-biasing (aka back-biasing) than you can in bulk (which suffers from too much leakage).  Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel, so it effectively acts like a vertical double gate transistor.  This facilitates the flow of electrons, leading to a higher voltage in the body, and faster switching of the transistor.

    (Courtesy: ST-Ericsson)

    (Courtesy: ST-Ericsson)

  • With FD-SOI, you can hit higher speeds with lower operating voltages. This is because the buried oxide layer prevents electrons from leaking away as they travel through the channel from the source to the drain (this sort of leakage is a major source of power consumption in 28nm bulk, which depends on doping to handle leakage). Interestingly, this graph shows ST-E going down to 0.5V – which is incredibly impressive.

    FDSOI vBulk graph

    (Courtesy: ST-Ericsson)

  • As the (now award-winning) folks over at ST and Leti described for us a few years ago, designing a good SOC involves using the right blend of low, standard and high-Vt devices according to the target application and how it’s being used at any given time.  The ST-E designers use this feature to apply different voltages independently to the top and the buried gates of the FD-SOI transistor, which effectively changes its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high-performance transistor to those of a very low-power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power. (You can’t do this with FinFETs, btw.)
    eQuad illustration blue       eQuad illustration red(Courtesy: ST-Ericsson)

Now are you starting to see why it’s a game changer?

ByAdministrator

ST-Ericsson’s 28nm FD-SOI SmartPhone/Tablet Chip at Vegas – a Great Start to 2013

What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013.

And it’s a game changer – for users, for designers, for foundries, and for bean counters.  Here’s why.

The NovaThor L8580 integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die.

eQuad

ST-Ericsson’s NovaThor(TM) L8580 on ST’s 28nm FD-SOI features a 2.5Ghz eQuad(TM) app processor with ultra-low power consumption. (Courtesy: ST-Ericsson)

In the eQuad CPU architecture, each processor core can operate as a high-performance core or a very-low-power core, depending on what’s needed at the moment. Since all the eQuad cores can adapt to the needs of the user at any given time, there’s no need for the dedicated low-power cores found in other multi-core CPU architectures. Remember, the 2.5GHz cores in the L8580 are the mobile industry’s fastest, or conversely, at 0.6V in low-power mode, the industry’s most battery-friendly. With all 2.5GHz cores working together, expect blazing high-performance when you’re doing something like browsing the web. But when phone’s your pocket, those cores will take barely a sip of power.

The NovaThor L8580 is essentially a straight port from 28nm bulk to 28nm FD-SOI of the (very successful) NovaThor L8540, with just a bit of tweaking to fully leverage cool things you can do with FD-SOI, like biasing to increase performance and conserve power.

For the folks designing smartphones and tablets (and ultimately for the end-user), that port to FD-SOI gets the NovaThor L8580:

  • CPUs running 35% faster and GPU and multimedia accelerators running 20% faster. In terms of multimedia performance, they’re supporting 1080p video encoding and playback at up to 60 frames per second, 1080p 3D camcorder functionality, displays up to WUXGA (1920×1200) at 60 frames per second and cameras up to 20 megapixels. (Hence their use of the descriptive “extraordinary”.)
  • 25% less power consumption than rival architectures when running at high-performance  levels – think Cooler Operation.
  • A low-power mode can deliver up to 5000 DMIPS at 0.6V – more than enough computing power for the majority of applications in everyday use. A key point here is that it enables stable SRAM operation at 0.6V – have you heard of anyone matching this? The result is that this low-power mode consumes 50% less power to deliver the same performance compared with alternative solutions in bulk CMOS.

It all adds up to big battery savings – this is the extra day CEO Didier Lamouche promised us in Barcelona last year when they announced this chip.

For the ST-E designers, most of the IP blocks were directly re-used from the bulk design, so the porting to FD-SOI was extremely simple and fast.

See ST-Ericsson’s live CES demo on YouTube

ST-Ericsson has posted an amazing video, filmed live at CES 13. In the first part of the demo (re: high-perf), on a Samsung Galaxy S3, they’ve got the Sky Castle 3D Graphics Demo launching twice as fast on FD-SOI as the bulk equivalent, and hitting 2.8GHz! And in the second demo (re: low power), they’re hitting 1GHz using just 0.636V, which would take 1.1V on bulk. Wow.

youtube

> Watch the video

For the manufacturing folks over at STMicroelectronics (and starting this year, at GloFo), FD-SOI is a planar technology that re-uses 90% of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex, so they’ve got lower cycle time and reduced manufacturing costs (bean counters take note, please). They also point out that the manufacturing tools for FD-SOI are much simpler than those required for FinFETs.

Wondering what’s next? The 14nm FD-SOI node is already in development, the ARM Cortex-A15‘s  on the radar, and the FD-SOI roadmap is already defined up the 10nm node.

Now you see why it’s a game changer?  Stay tuned.  The next ASN blog will take a deeper look at how ST-E designers are implementing the FD-SOI technology.

And from all of us here at ASN, we wish you a very happy, healthy and prosperous New Year.

> View part 2

ByGianni PRATA

STMicroeletronics announced its 28nm FD-SOI Technology is ready for manufacturing in its leading-edge Crolles fab

ST CrollesSTMicroeletronics announced its 28nm FD-SOI Technology is ready for manufacturing in its leading-edge Crolles fab.  At the SOI Consortium FD Symposium,  ST presented silicon-verified process technology that delivers 30% higher speed and up to 50% improvement in power.  ST’s FD-SOI Technology Platform encompasses the availability of a feature-complete and silicon-verified Design Platform, including the full set of foundation libraries (std-cells, memory generators, I/Os), AMS IPs and high speed interfaces), and a design flow ideally suited for developing high-speed and energy-efficient devices. ST has found porting Libraries and Physical IPs from 28nm Bulk CMOS to 28nm FD-SOI to be straightforward, and the process of designing digital SoCs with conventional CAD tools and methods in FD-SOI to be identical to Bulk.  In a separate announcement on corporate strategy, the company re-affirmed its commitment to FD-SOI technology.

ByGianni PRATA

A spokesperson for the newly-named Novati Technologies fab in Austin, TX says that in addition to silicon, they will be supporting various substrates including: SOI, quartz, glass, etc

A spokesperson for the newly-named Novati Technologies fab in Austin, TX says that in addition to silicon, they will be supporting various substrates including: SOI, quartz, glass, etc. The facility, which was formerly owned by SVTC, was recently acquired by 3D-IC specialists Tezzaron Semiconductor.

ByGianni PRATA

The Paul Scherrer Institute reports that they have achieved strained silicon nanowires with the highest strain ever

Strained silicon nanowires

(Graphics: Paul Scherrer Institut/ R. Minamisawa)

Starting on SOI, the Paul Scherrer Institute reports in Nature that they have achieved strained silicon nanowires with the highest strain ever (4.5% elastic strain).

The principle of the method used for achieving a high stress in silicon: Firstly, the forces act in all directions in the silicon layer. If small parts of the layer are then etched away to create a thin wire, the forces act along the wires so that a high stress is created within them.

ByGianni PRATA

TowerJazz saw “a large amount of SOI design activity” in 2012

TowerjazzThe CEO of TowerJazz recently told analysts that in 2012, the company saw “a large amount of SOI design activity”, which he says will fuel revenue growth in 2013. Smart phone antenna switches that handle 8 to 14 different bands are moving from gallium arsenide to SOI, he explained.

ByGianni PRATA

Researchers from the NIST Center for Nanoscale Science and Technology have developed a nanophotonic motion sensor

NIST Nanophotonic Motion SensorTaking a new approach to SOI-MEMS, researchers from the NIST Center for Nanoscale Science and Technology have developed a nanophotonic motion sensor.  Enabled by cavity optomechanics, it can measure the mechanical motion between two nanofabricated structures with a precision close to the fundamental limit imposed by quantum mechanics. Fabricated on a silicon chip at low cost, the device provides a model for dramatically improving MEMS-based sensors such as accelerometers, gyroscopes, and cantilevers for atomic force microscopy.

ByGianni PRATA

The multi-core CPU in Nintendo’s new Wii U is fabbed by IBM on 45nm SOI

Wii U console blackAs noted in ASN last year, the multi-core CPU in Nintendo’s new Wii U, which hit the shelves in November 2012, is fabbed by IBM on 45nm SOI.

ByAdministrator

Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM

If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium.

As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s been doing these symposia during major conferences for going on four years now, and lively debates always ensue.

Hilton San Francisco Financial District

(Courtesy: Hilton Hotels & Resorts)

This next FD Tech symposium happens the first day of the IEEE’s IEDM conference in San Francisco – Monday, December 10th at 8:15pm. Conveniently, it’s also taking place in the same building – at the SF Hilton.

Top technologists from STMicroelectronics, ST-Ericsson, IBM, ARM, Altera, LETI, Soitec, MEMC and others will be debating comprehensive Fully-Depleted Technology solutions.

But perhaps most importantly, we’re going to get the first product-level benchmarking results of 28nm FD-planar for mobile SoC and FPGA applications.  That’s silicon proof straight from the companies who are doing it.

If you’ve been following recent ASN postings from STM, ST-Ericsson, IBM and others, you know these folks are really excited about the results they’re seeing.

Here’s a peak at the presentations planned for the symposium:

  • Planar Fully-Depleted Technology at 28nm and below for extremely power-efficient SoCs:  SoC level 28nm Planar Fully-Depleted silicon results
    By Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics
  • Evaluation and benchmarking of 14nm planar Fully-Depleted Technology for FPGAs
    By Jeff Watt, Ph.D. Fellow, Technology Development, Altera Corporation
  • Challenges and comparisons of designing power-efficient SoCs with planar Fully Depleted transistors and FinFETS
    By Rob Aitken, ARM Fellow
  • Second-generation FinFETs and Fin-on-Oxide
    By Ed Nowak, IBM Distinguished Engineer and Device Chief Designer, Semiconductor R&D Center, IBM Systems and Technology Group

The presentations will be followed by a Q&A.

Admission is free, but space is limited, so you must reserve in advance – click here to go to the special registration site.

To recap, it’s the:

Fully-Depleted Transistors Technology Symposium
Hilton San Francisco Union Square Hotel (333 O’Farrell St.)
Monday, December 10th, 2012
8:15pm to 10:30pm

Food & refreshments will be provided.

We won’t all be in San Francisco, so if you can’t get there, the presentations will be posted on the SOI Consortium website (you can also get the presentations from previous events there, too, as well as excellent white papers).

If you do go and want to share your reactions on Twitter, use #FDchipTech and @soiconsortium.

This will be a great event – don’t miss it!