GlobalFoundries has announced availability of its 45nm RF-SOI technology (read the press release here). Dubbed 45RFSOI, the company says it’s the first 300mm RF solution for next-gen mmWave beamforming applications in future 5G base stations and smart phones.
The technology supports mmWave spectrum operation from 24GHz to 100GHz band, 5x more than 4G operating frequencies.
Skyworks’ CTO Peter Gammel says that the 45RFSOI process, “…is enabling Skyworks to create RF solutions that will revolutionize emerging 5G markets and further advance the deployment of highly integrated RF front-ends for evolving mmWave applications.”
The news was quickly picked up by publications across the industry, with EETimes noting that RFSOI has been a big GF success story.
Production will be at the company’s East Fishkill fab. The PDKs are available now.
The 45RFSOI news follows hard on the heels of GF’s announcement a few days prior that the company is teaming up to build a fab offering 22nm FD-SOI in western China, that it’s expanding its Dresden FD-SOI capability by 40 percent, and that it’s adding new RF-SOI capabilities to its fab in Singapore.
GlobalFoundries is a member of the SOI Industry Consortium.
IEEE S3S Conference
10-13 October 2016
Hyatt Regency San Francisco Airport
IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference
Theme: Energy Efficient Technology for the Internet of Things
Late News submissions open and Advance Program available
The IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.
This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.
We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.
Our Keynote speakers are decision-makers from major industries:
Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.
Applications will be illustrated in our session dedicated to SOI circuit implementations.
You can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.
And you still have time to actively participate by submitting a late news paper before August 31st.
The conference has a long tradition of allying technical and social activities.
This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.
With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.
Deadline for Late News submissions is
August 31st, 2016
For further information, please visit our website at s3sconference.org or contact the conference manager:
Joyce Lloyd • 6930 De Celis Pl., #36
Van Nuys, CA 91406
T 818.795.3768 • F 818.855.8392 • E email@example.com
Don’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.
As of this writing, the following keynote speakers have been confirmed:
Invited speakers include:
As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.
Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :
For current information on the conference visit the S3S website at: http://s3sconference.org/
LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.
Is RF-SOI the same thing as RF on FD-SOI? No, it’s not. However, the runaway success of RF-SOI and the growing list of recent announcements related to FD-SOI with integrated RF has lead to some confusion in the press and social media. The two are different technologies, addressing different markets, and built on two very different types of SOI wafers. The use of one technology or the other depends on the requirements of the targeted RF application.
For the non-technical reader, here is a bit of basic background. At the most simplistic level – RF: radio frequency – is part of the analog family, and as such is all about waves. And when you talk about waves, you talk about losses over distance (attenuation), speed, wavelength and frequency – which is why the RF design has a rep of being something of a black art. The distance to cover, the power envelope and the amount of data to carry over that distance (and of course, the cost) determine the chip solutions. An important part of the RF chip solution is the choice of the wafer substrate itself.
So here’s a quick primer to help sort out what’s what. Please bear in mind, though, that this is a fast-evolving world, so what you’re about to read is not a definitive and forever what’s what – but more of a general (and simplified) “this is how it is currently shaking out”.
RF-SOI – Talk to the Tower
When it comes to using your mobile device for data transmission over a 2G, 3G, 4G/LTE/LTE-A (and next, 5G) network, you still need dedicated RF front-end modules (FEMs). FEMs handle the back-and-forth of signals between the transceiver and the antenna. They contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. Traditionally, they were built on gallium arsenide substrates. But more and more, the multiple chips in FEM chipsets are being reduced to single SOCs built on a special class of high-resistivity SOI wafers. This is the realm of RF-SOI. The wafers for RF-SOI are designed specifically to handle the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances.
The latest standards (LTE-A and 5G) raise the stakes ever higher, requiring mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)
For RF designers, that means choosing substrates that favor low RF loss and high RF linearity. A couple of years ago, SOI leader Soitec, in partnership with UCL, brought breakthrough RF-SOI wafer technology to the market (read about that here). Now, a few generations later, Soitec estimates that one billion RF devices are produced each quarter using their advanced and enhanced Signal Integrity™(eSI)wafers for RF. In fact it would be nigh near impossible to find a smartphone that doesn’t have an RF FEM based on RF-SOI wafer technology.
Here at ASN, we’ve covered many of the leaders in RF-SOI FEMs over the last few years. Click on any of these names to get an idea of what they’re doing: IBM (now part of GlobalFoundries), Peregrine, SkyWorks, TowerJazz, ST, Qorvo, Sony, Qualcomm, Grace, Toshiba and MagnaChip. To learn more about the latest developments in wafer technology for RF-SOI, click here. With demand soaring, Soitec’s most advanced RF-SOI wafers are now also being produced by Simgui in China – read about that here.
In fact, the cover story and technical features of the October 2015 issue of the prestigious Microwave Journal is dedicated to RF-SOI – click here to read it.
So in terms of terminology, that’s “RF-SOI”. Now let’s look at how RF on FD-SOI is different.
RF in FD-SOI – for digital integration
When we talk about RF in FD-SOI, we’re typically talking about some RF functionality being integrated into SOCs that are essentially digital processors. True, you can integrate RF functionality into an SOC built on planar bulk (it’s generally agreed to be a nightmare in bulk FinFETs, though). But you can integrate RF into your digital SOC much more easily, efficiently and with less power if you do it in FD-SOI.
RF/analog has a (well-deserved) rep of being the most challenging part of chip design. Analog/RF devices are super sensitive to voltage variations. The digital parts of a chip, which have strong, sudden signal switching, can raise havoc with nearby analog/RF blocks. This means that the analog/RF designers have to care acutely about gain, matching, variability, noise, power dissipation, and resistance. They use all kinds of specialized techniques: FD-SOI makes their job a lot easier (good explanation in slide 8 here). What’s more, FD-SOI’s analog performance far exceeds bulk.
What sort of chips are we talking about? For now, we’re talking about processors for mobile devices, for IoT, for automotive, for consumer electronics. When we say “RF in an FD-SOI SOC”, we’re currently talking about chips that are connecting over a relatively short distance to a nearby box or device (<100m for local WiFi, or a few meters for Bluetooth or Zigbee, for example).
ST’s new set-top-box processors on 28nm FD-SOI (read about them here) are a great example. They are the first on the market integrating 4×4 802.11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This means the set-top boxes can reliably serve lots of HD video via WiFi to multiple users throughout the house (hopefully ending the cry: “Who’s hogging all the Wifi?!?”). ST credits their 28nm FD-SOI silicon technology with providing that highly-efficient RF, state-of-the-art WiFi performance and robustness required for reliable video delivery inside the home.
For RF on FD-SOI – as in other FD-SOI apps – designers use SOI wafers with ultra-thin silicon, ultra-thin insulating BOX and phenomenal top silicon thickness uniformity. These wafers are not the special high-resistivity wafers used in RF-SOI. Rather, they are the latest generations of the same (amazing!) FD-SOI wafers that Soitec introduced in 2010. (For an excellent, in-depth interview with the Soitec FD-SOI wafer guru on the supply chain and the most recent developments, click here.)
This is the type of wafers that GloFo, ST, Samsung, Freescale, Sony, several other companies in Japan and many more around the world are using when they say they’re doing RF on FD-SOI. Bear in mind that this level of SOC integration is fairly new (Samsung and TSMC just announced RF integration into SOCs for the first time in 2014 on 28bulk). But using FD-SOI technology and the corresponding ultra-thin SOI wafer substrates makes life much easier for the RF folks on the design teams, gets far better performance and far lower power at a much more attractive cost.
Further ahead, FD-SOI is also a candidate for transceivers and baseband/modem SOCs, which require high-performance digital and analog/RF integration. But even with transceivers on FD-SOI, you’ll still need the FEM on RF-SOI to handle the interface.
So, that’s the current difference between RF-SOI and RF on FD-SOI.
Hope that helps to clear things up?
A very successful two-day forum on FD-SOI and RF-SOI in Shanghai (September 2015) featured presentations from CEOs, CTOs and VPs at GF, ST, Leti, ARM, Verisilicon, Synapse Design, SITRI, Skyworks, Freescale, TowerJazz, Soitec, Qorvo and many more. Most of the presentations are now available on the SOI Consortium Website, and the rest are expected shortly, so keep checking back.
To download the “Design for FD-SOI” presentations, see the list here.
To download the “RF-SOI Workshop – Interconnected World” presentations, see the list here. (Presentations from all of the major SOI wafer suppliers are also available on this page.)
All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.
The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.
The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.
As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.
As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.
But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year. In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.
The RF-SOI Juggernaut
SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.
In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.
In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.
In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.
In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.
14nm SOI-FinFETs Get Real
In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs. SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)
They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.
For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.
Representative bulk-based (junction-isolated) and SOI-based (dielectric-isolated) fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET. (Courtesy: IBM)
Manufacturing a FinFET on SOI also enables a more ideal fin profile. In turn, this near-ideal shape delivers performance well in line with the “theoretical” benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.
IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.
The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.
So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!
The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.
The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).
Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.
The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)
The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.
sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).
An impressive hot topics session was dedicated to RF CMOS.
J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.
Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.
The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).
The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.
The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.
3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.
The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.
Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.