Tag Archive Smart Cut

LTE-A/5G: Bring it on. Next-gen Soitec eSI90 wafers predict & improve RF performance.

The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.

SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit.  That’s for 2G, 3G and now 4G and LTE.

But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.

Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.


SOI wafers. (Courtesy: Soitec)

But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.

Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).

The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).

So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.

Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.

To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.

The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.

When it comes to next-gen mobile design, innovation really does start at the substrate level.

Soitec and Simgui (China) Partner on SOI Wafer Production for RF and Power Apps

Soitec and Simgui (Shanghai, China) are partnering on SOI wafer production for RF and power applications. The newly signed deal (read press release here) includes a licensing and technology transfer agreement. Simgui will establish a high-volume SOI manufacturing line using Soitec’s proprietary Smart Cut™ technology to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide. Beyond this initial cooperation, the two companies plan to expand their collaborative efforts in the future to take advantage of their synergies.

Interview: Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

Interview with : Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

With FD-SOI entering the mainstream, fabless designers have been asking about the wafer supply chain. ASN spoke about it with Christophe Maleville, Sr. VP of the Microelectronics business unit at Soitec, the world’s leading SOI wafer producer.

MalevilleChristophe Maleville has been Senior Vice President of Soitec’s Microelectronics BU since 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as Vice President, SOI Products Platform at Soitec, working closely with key customers worldwide. He has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from the Grenoble Institute of Technology and obtained an Executive MBA from INSEAD.


Advanced Substrate News (ASN): With the recent news that Samsung has joined the ranks of foundries offering high-volume 28nm FD-SOI, can you tell us why customers are turning to FD-SOI?

Christophe Maleville (CM):   The short answer is that they consider FD-SOI provides a much better combination of power consumption, performance and cost than any alternative for the technology node they target.

At 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node. And for some products at least, using this enhanced 28nm is actually a better choice than going to the next node.

Then 20nm FD-SOI (also called 14FD) will provide the kind of performance and energy efficiency promised by 16nm/14nm FinFET, at a lower cost than even 20nm planar bulk CMOS.

ASN: Who are the wafer suppliers and what kind of capacity is there?

CM:  There are three major suppliers serving the FD-SOI market:  Soitec, Shin-Etsu Handotai (SEH) and SunEdison (formerly MEMC).  SEH is the world’s biggest producer of silicon wafers. Soitec is the world leader in SOI wafer manufacturing. SunEdison has been supplying SOI wafers for over a decade.  SEH and Soitec use Soitec’s Smart CutTM manufacturing technology.  However, each company fine-tunes the technology to meet to its customers’ specifications.

For our part, I can add that Soitec has two distinct production sites. We source the raw bulk base and donor wafers (from which the FD-SOI wafers are fabricated under our FD-2D product name) from a diverse group of suppliers, which enables us to optimize the quality of our wafers, combining the best wafers for donor and handle. We are converting capacity at our plants in France and Singapore to meet expected FD-SOI demand.

The industry’s current installed capacity is in the range of one million 300mm SOI wafers/year. However, the wafer suppliers are ready to expand capacity to meet market demand, so we could easily reach two million in well under a year, and continue ramping rapidly from there. It’s perhaps worth understanding that the equipment and materials needed to manufacture SOI wafers are standard industry hardware and materials – there are no exotic parts to the manufacturing equipment nor rare materials that could cause bottlenecks in the processes we use to manufacture the SOI wafers.


ASN:  FD-SOI wafers are known to have very stringent requirements. Can you review those here?

CM: SOI wafers are subject to many of the same criteria as other advanced wafers, such as flatness and defectivity.  The additional parameters for FD-SOI wafers, which require tight control, are:

  • the top silicon thickness,
  • the top silicon uniformity,
  • and the BOX (Buried OXide – the insulating layer).

The thickness of the top silicon of the SOI wafers (denoted as TSOI) we provide ranges from 10 to 16nm, depending on customer requirements and node. The top silicon essentially “pre-defines” the channel. But, it’s important to remember that the starting thickness of the top silicon in the wafer has to be a little thicker than you’ll find in the processed device, as a few nanometers of top silicon is etched away during device processing.  So in a TEM of a 28nm FD-SOI transistor, you might see TSOI of 7nm, but the wafer that it started on would have had top silicon of 12nm, to accommodate the 5nm that would be etched away during processing.


In FD-SOI, the BOX layer is actively leveraged in back biasing, wherein you’re essentially creating a second (“back”) gate. This makes the parameters of the BOX layer especially important for ultra-low power operation.


ASN:  Why do the wafers have to be so uniform?

CM: With respect to the top silicon uniformity, uniform thickness is crucial to controlling transistor threshold voltage (Vt) variability. The top silicon uniformity of Soitec’s FD2D wafers is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. For the BOX thickness, we can offer thicknesses ranging from 10nm to 25nm, again depending on the customer’s approach.  Technology’s like ST’s UTBB (ultra-thin body and Box) leverage very thin BOX for body biasing, which gives them a big edge in performance and low-power.


ASN: Are suppliers really ready to produce these wafers in high volumes?



CM:   Yes, at Soitec we announced that we were ready for FD-SOI wafer volume back in 2012. Having met the specifications, we focused on offering good yields to our customers. In fact, the yield for Soitec’s FD-2D substrates is already reaching the yields we have for our wafers for partially-depleted SOI, which we’ve been selling for over a decade. This was critical to our clients, in order for them to have a fully-qualified 28nm FD-SOI process using wafers from Soitec and other suppliers. The results that customers have demonstrated in terms of variability (especially for Vt distribution, which is closely linked to wafer uniformity) and the electrical results show the wafers fully meet their production requirements. Smart CutTM technology enables us to manufacture according to these stringent requirements, and our years of experience let us move into high-yield, high-volume FD-SOI wafers at the right cost and at the right time for the market.


ASN: Can wafer suppliers adapt to the fluctuations in demand seen in very high-volume markets?

CM:  The SOI ecosystem is already familiar with the mobile market, which in terms of volumes is currently the world’s biggest market – and certainly is volatile. SOI wafers are widely used in RF, particularly in RF switches, where over 70% of the devices for smartphones are built on SOI.  While wafers for RF have some specific parameters, generally speaking the FD-SOI wafers are produced using similar technology, flow and logistics as our SOI wafers for RF – so for us, it’s just another segment of the mobile market.


ASN: Some say that managing buffer wafer stocks would be too complicated for the foundries – is that true? Can you explain briefly how the wafer supply contracts are typically structured?

CM: The SOI supply chain is no different than the bulk supply chain. As such, the structure of the wafer supply model is similar to supply chains in other industries. The foundries don’t have to fully own and manage a costly buffer stock of wafers. In the case of large customers, they typically negotiate a supplier-managed inventory dedicated to their needs, and they only pay when they actually consume parts from this stock.  This kind of buffer also helps smooth out possible rapid fluctuations of the demand.


ASN:  For its latest report (which found that FD-SOI is the most cost effective approach for the 28nm an 14nm nodes), IBS uses the figure of $500/wafer. Is that realistic?

CM: While of course pricing depends on commercial negotiations, 500USD in volume for 28nm FD-SOI wafers is definitely a sensible budgetary price: conservative and achievable. And starting at the 28nm node, as IBS points out, using SOI wafers results in similar cost for processed wafer when compared to typical 28nm bulk reference – a phenomenon that gets even better with scaling to 14nm. And although the specifications for the 14nm wafers are more exigent, we confirmed that substrate cost increase will not exceed 10%.


ASN: What about the future – will the wafers be able to meet the specs for the 10nm market? What about the move to 450mm wafers?

CM: ST has indicated a 3-node FD-SOI roadmap: 28nm-14nm-10nm. Working with our partners, we’ve shown that from the perspective of the wafer specs, we can fully comply with the parameters required to support this. For example, we have engineered strained silicon that meets the 10nm node specifications for boosting mobility – there are no show stoppers here. In terms of 450mm, while it seems unlikely that the move is imminent within the next few nodes, we are full participants in the industry’s R&D efforts, and have demonstrated that with our Smart Cut technology using the standard toolset found in CMOS FEOL, we can produce 450mm versions of our FD2D wafers, when and if the need arises. We’re ready whenever the industry is.

Interview: Leti CEO Laurent Malier on FD-SOI and more

CEA-Leti is one of the world’s most important research institutes for micro- and nano-electronics. Key enabler to the greater SOI-based community, they’re the quiet mega-partner behind everything from Soitec’s Smart CutTM technology for SOI wafer manufacturing to the design and chip manufacturing technology in today’s FD-SOI revolution. Leti’s work always reaches far into our industry’s future.  ASN had a chance to catch up with CEO Laurent Malier to see what’s up and what’s next.


Laurent Malier, CEO of CEA-Leti and President of the Association of Carnot Institutes

Advanced Substrate News: For those who don’t know Leti well, can you give us a general introduction, and tell us how you work with industry?

Laurent Malier: Leti focuses on micro- and nano-technologies and their applications. Our goal is to create innovation in those domains and transfer it to industry. We are part of the CEA, a French government-funded technological research organization. Seventy-five percent our 250M€ budget comes from industrial contracts.


Since we cover everything from silicon to applications, Leti addresses microelectronics, embedded software and applications in consumer, automotive, health-care, environment, space, safety and security, wireless and smart-devices markets.



Leti has worked with more than 365 industrial partners worldwide through one-to-one  collaborations, collaborative projects and common labs. We provide access to advanced technology platforms (we have 8,000m² of cleanroom space) and offer broad scientific and technological support.

ASN: Can you give us a bit of history on Leti’s role in SOI in general, and FD-SOI in particular?

LM: Leti has been involved in SOI since the early days with Leti researcher Michel Bruel’s original patent on the Smart Cut™ technology for manufacturing SOI wafers. That was in 1991, and the technology was licensed to Soitec in 1992. Leti’s active involvement in advanced on-oxide substrates development has continued since then. We have also been a pioneer in SOI-focused compact modeling. A Leti spin-off company called Soisic was created in 2001 and later bought by ARM to offer SOI-based design.

Last December, Leti announced Leti-UTSOI2, the first complete compact model for FDSOI. It enlarges the physically described bias range for designers and is available in all major SPICE simulators.

For wireless markets, Leti has taken part in the development of RF-SOI for 130 and 65nm from high-resistivity wafers and process integration to models.

Leti’s current SOI knowledge starts with the substrate, embraces the device and extends to the full design platform with TCAD support, compact modeling and design and conception.

Our strong focus on SOI devices and technology has produced original breakthroughs, ranging from the demonstration of interest in thin BOX substrate to multi-Vt design, and benefits from built-in power-performance trade-off tuning capabilities.


(Full PDF available here.)

ASN: Can you tell us more about Leti’s current and future contributions to FD-SOI?

LM: Fostered by Grenoble’s unique ecosystem, where substrate suppliers are located near IDMs and design companies, Leti’s work spans the whole range of activities related to SOI. Leti’s current contribution to FD-SOI covers the full spectrum: materials, process, integration, device, modeling, architecture and systems.


Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

Combining research and manufacturing experience, from a digital point of view, Leti supports 28nm FD-SOI at STMicroelectronics with an on-site team of more than 60 people. Leti has been part of the IBM Alliance based in Albany, NY since 2008. We’ve played a key role in 14nm FD-SOI development, with teams based in Albany, Grenoble and Crolles.

And more than anybody, Leti is now shaping 10nm FD-SOI. That’s what we do: we are always working well ahead of the industry!

In summary, Leti serves the global SOI ecosystem.

ASN: Can you give us a peak at Leti’s work on future devices, structures, substrates and so forth?

LM: With respect to10nm FD-SOI, Leti is currently addressing two main challenges. The first is how to implement performance boosters; and then how to optimize the smart use of back biasing to keep on leveraging SOI technology’s big competitive advantage in energy efficiency.

And what will be the next device? Definitely it will have to enable energy-efficient circuits. The race to lower overall energy consumption at no performance penalty has begun. Within this context, Leti is actively preparing the for future by evaluating potential scaled SOI architectures. Trigate, nanowires and stacked nanowires are options envisioned to pursue SOI CMOS-based scaling. Leti is also thoroughly investigating new device concepts to combine better performance with more energy-efficient hybrid circuits.

Leveraging our SOI expertise, Leti is paving the way to enable the 3D monolithic integration where layers of transistors are stacked with a lithographic alignment resolution: it allows connecting active areas at the transistor level. This revolutionary way of thinking about next nodes enables less consumption with better performance and is a unique technological tool to enable III-V and high mobility materials hybrid integration.

ASN: Will we see more Leti spin-offs?

LM: Most definitely. One of Leti’s goals is to foster the creation of startups that leverage our technological innovations. That creates jobs and value in the local economy, and opportunities for the electronics industry, globally. Leti is one of the world’s leading research institutions for startup creation: Soitec, Sofradir, ULIS, Movea, APIX Technology and Aledia are some of the companies that Leti has launched over the years.

We certainly intend to step up the pace. Last year, our recently revamped startup program launched Wavelens, which delivers compact MEMS-based optical solutions for the mobile phone market, and Primo1D, the ‘E-Thread®’, company. And ISKN, one of our currently incubated companies, had one of the most successful Kickstarter campaigns last year. It raised close to $350,000, almost 10 times its original goal, for iSketchnote, its smart iPad cover. So I think we can say there will be more Leti startups in the months and years to come.

IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.


So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

Which wafers for energy-efficient, fully-depleted transistor technologies?

To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.

To continue scaling CMOS technology, new approaches are needed and the industry is turning to ultra-thin body, “fully depleted” (FD) transistors. These may retain a planar architecture (Fig. 1b) or go tri-dimensional (Fig.1c), in which case current flows in vertical ‘fins’ of silicon.

In both cases, in contrast with traditional technology, the current between source and drain is only allowed to flow through a very thin silicon region, defined by the geometry of the transistor. In addition, such transistors can eliminate or alleviate the need for implanting “dopant” atoms into their channel.

The physics of FD transistors allows their behavior to be greatly improved – making it possible to continue creating more complex chips with better performance and, most importantly, with power consumption kept under tight control.

FD transistors

Figure 1: Contrary to conventional CMOS (a), with planar FD (b) and tri-dimensional FD (a.k.a. FinFET) (c), the current is confined within a thin layer of silicon. [notional diagrams – not to scale]

The semiconductor industry is introducing planar FD (also referred to as FD-SOI) starting at the 28nm node, with first IC product samples scheduled for the end of 2012. Tri-dimensional FD or FinFET, on the other hand, is expected below 20nm in foundries.

Wafers for fully-depleted technology

With FD technology, either planar or tri-dimensional, the transistors are either necessarily or advantageously fabricated on innovative silicon-on-insulator (SOI) starting wafers. These wafers consist of a very thin layer of crystalline silicon, separated from a silicon base by a high-quality (and optionally ultra-thin) oxide. Soitec’s Smart CutTM technology is used to produce them and is licensed to third-parties to ensure multi-sourcing options.

Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for the planar and FinFET implementations of FD transistors. Two different wafer product lines are available to serve the needs of these two technology flavors.

FD-2D – An early and evolutionary path to fully-depleted technology

Planar FD technology puts tight requirements upon starting wafers to deliver all its benefits: for example, top silicon layer thickness must be uniform to just a few Angstroms. Today, Soitec’s FD-2D product line meets these needs in a cost-effective way and makes planar FD technology a reality.

Cross-section of a planar FD transistor fabricated on an FD-2D wafer

Figure 2: Cross-section of a planar FD transistor fabricated on an FD-2D wafer [notional – not to scale]

Figure 2 outlines the structure of a transistor fabricated from an FD-2D wafer. For the 28nm technology node, the buried oxide thickness has been set to 25nm; the ultra-thin top silicon allows fabrication of transistors with 5nm to 8nm silicon under the gate. Future generations can leverage even thinner buried oxide layers, contributing to making this technology scalable to subsequent nodes.

By enabling a planar implementation of fully depleted technology, these wafers offer the opportunity to access the benefits of FD today – there is no need to anxiously await FinFET and the 16nm/14nm technology node. Adopters of planar FD are announcing very substantial performance and leakage gains as well as impressive improvements of energy efficiency, along with exceptional performance maintained at very low power supply [Ref.1-3].

Owing to the great compatibility of planar FD with conventional CMOS, designers retain the flows and tools they would use with the latter. Furthermore, chip manufacturers use the same production lines as well as extremely similar process steps. Finally, different studies indicate that the cost of ownership of chips based on planar FD is extremely competitive compared to any alternative.

FinFET – Transition facilitated by innovative FD-3D wafers

A FinFET transistor consists of one or several fins of silicon, electrically isolated from the substrate, around which the gate wraps.

FinFET on bulk silicon wafer

Fig. 3a: FinFET on bulk silicon wafer (one fin shown) [notional – not to scale]

One solution (Figure 3a) to manufacture FinFETs consists of starting from a traditional bulk silicon wafer and completely handling fin creation and isolation through the CMOS process.

FinFET on FD-3D wafer

Fig. 3b: FinFET on FD-3D wafer (one fin shown) [notional, not to scale]

The alternative (Figure 3b) is to start from a “FinFET-friendly” wafer such as Soitec’s FD-3D, which pre-defines some of the fin characteristics and, with its buried oxide, natively embeds the electrical isolation, thus simplifying the CMOS process.

Specifically [Ref. 4-5], FD-3D wafers help obtain clearly defined and reproducible fin height and width, consistent alignment of gate, source, drain and channel, and provide optimal isolation of each fin.  In addition, it is possible to implement undoped fins if desired – thus cutting variability related to random dopant fluctuations.

Overall, and especially as dimensions will continue to shrink beyond the 16nm node, FD-3D wafers offer to facilitate control over key parameters of FinFETs as well as simplify the fabrication process. They represent an opportunity for chipmakers to make the most of FinFET technology in terms of power/performance ratio and leakage power at chip level. They are also a worthwhile proposition to reduce the industrialization challenges and optimize the total cost of ownership.

Longer term

Looking beyond the 10nm node, technology based on germanium and III-V compounds is being actively researched. In parallel, the transition of leading-edge chip production to 450mm diameter wafers is expected for the end of this decade.

In this context, the Smart Cut™ layer transfer technology for manufacturing innovative wafers may again prove extremely valuable by enabling independent control over various optimization knobs. For example, transferring a thin layer of high-quality, optimized III-V material onto a low-cost handle wafer (silicon or other), with an optimized interfacing layer, could be an interesting option.


Fully depleted silicon technology is coming. The question is how fast and how easily this transition can be accomplished: innovative wafers provide part of the answer.

With FD-2D, they enable a planar implementation, providing the semiconductor ecosystem with an early and low-risk path towards optimal performance and power efficiency across all use cases, as soon as the 28nm node.

With FD-3D, they can help efficiently address some key challenges of FinFET technology and make the most of it.

Looking further ahead, the Smart CutTM technology will continue to simplify the implementation of the next silicon technology breakthroughs.


[Ref.1]    White Paper, “Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond”, STMicroelectronics –  http://www.soiconsortium.org/about-soi/white-papers.php

[Ref.2]    ST Ericsson Technology Blog, May 2012: “FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2”,  http://blog.stericsson.com/blog/2012/05/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-%E2%80%93-part-2-2/

[Ref.3]    “MWC ST-Ericsson Media & Analyst Briefing”, February, 2012 –  http://www.stericsson.com/investors/Analyst-Event-Presentation-MWC-12.pdf

[Ref.4]    « SOI Value in IBM Silicon Technology », Oct.2011 – http://www.gsaglobal.org/3dic/docs/20111019_IBM_SOI_Value_GSA.pdf 

[Ref.5]    “SOI versus bulk-silicon nanoscale FinFETs”, Jerry G.Fossum et al., SSE Volume 54, Issue 2, Feb. 2010.

Wafer Leaders Extend Basis for Global SOI Supply

Soitec Shin-Etsu

It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.

SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.

With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.

As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”

SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”

Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.

SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.

With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”

As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”

Soitec SOI wafers

Beyond logic

The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.

The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.

So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.

Soitec Smart Cut

This illustration shows how Smart Cut, Soitec’s proprietary engineered wafer technology, works. The industry standard, this revolutionary wafer bonding and layer splitting processes makes it possible to transfer a thin layer of material from a donor substrate to another substrate, overcoming physical limitations and changing the face of the substrate industry. The Smart Cut technology was originally developed by the CEA-Leti. Soitec holds exclusive exploitation of CEA-Leti rights into the Smart Cut technology, including the right to sublicense to SEH. The technology was made viable for SOI high-volume commercial production by Soitec, and is now protected by more than 3,000 patents owned or controlled by Soitec.

Soitec and Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets

World-leading advanced substrate maker Soitec and compound materials leader Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets. Soitec applies its Smart CutTM layer-transfer process to Sumitomo’s bulk GaN wafers to generate engineered wafers with the same thermal expansion (CTE) as standard GaN wafers but at lower costs.

Driving SOI Cost Reductions

The SOI cost structure is on target for penetrating new markets – especially the all-important mobile markets. Volume customers can anticipate 300mm SOI wafer prices in the $500 range.

Many factors are enabling the cost structure for reaching the $500 SOI wafer.

As the leading SOI wafer manufacturer, Soitec has been driving optimization of its Smart Cut™ manufacturing technology for increased efficiency and continuously improving yields. Read More

Inventor of Smart Cut™ Technology Honored

The IEEE has conferred the Cledo Brunetti Award on Dr. Michel Bruel.

At a ceremony at the IEDM in San Francisco, the IEEE Board of Directors gave the 2008 Cledo Brunetti Award to Dr. Michel Bruel for his invention of the Smart Cut™ layer transfer technology that enabled widespread adoption of SOI for CMOS circuits. One of the industry’s greatest honors, the award recognizes outstanding contributions to miniaturization in the electronics arts. Read More