Some really innovative start-ups presented chips they’re doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We’ll cover those here in Part 3 of ASN’s coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion.
BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who’s designing chips on FD-SOI, and VLSIresearch explained why. You can read that here.
Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.
Ineda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They’re using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes.
In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud.
Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN’s coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor’s talked about their roadmap.
eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July ’18.
Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic.
Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec’s Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting.
In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers & acquisitions would not solve the problem, they’ve opened a second round, targeting another $160 billion.
China’s two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals.
IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said.
The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists.
QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you’ve got one set of IP, and you can decide at runtime where you’re going for low power or high performance. With a lot of power domains, you see the benefits at the system level.
GF VP Dave Eggleston said they’re seeing early adopters of eMRAM, especially for wearables with RF and low power.
ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores.
Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”.
It’s not too late for FD-SOI: it’s perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they’re happy to focus on companies still on the older nodes.
The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You’ve got more potential customers, and your volume runs can be bigger.
In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day’s three take-aways:
“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.
The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.
It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations. The next post(s) will cover the afternoon session. Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.
As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.
In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.
“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.
They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.
FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.
NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.
Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.
iMX and FD-SOI enable scalable solutions, he concluded.
What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.
Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.
But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.
Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!
For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.
SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.
Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”
According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.
For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.
Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.
With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT. A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.
And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”
Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.
So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.
China Mobile is the world’s largest* telco. So when Danni Song, one of the company’s high-level project managers presented at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai, you can bet people listened. With each new slide, a glowing sea of cell phone cameras rose over the heads of the audience in the huge, packed ballroom.
Over the last month, there’s been a lot more coverage of 5G in the press (especially after the recent Mobile World Congress (MWC) – check out Junko Yoshida’s EETimes piece for example). For ASN readers who want to know more about 5G and RF-SOI in China, here’s a reminder that Song’s presentation, and many of the others given by leading companies at the RF-SOI Workshop last fall, are now posted on and freely available the Consortium website Events page. Click here for the listing and links.
The theme of the workshop was IoT, mobile, 5G connectivity, and mmW. As Dr. Xi Wang, Director General of SIMIT/CAS (the Shanghai Institute of Microsystem & Information Technology in the Chinese Academy of Sciences), said in his opening keynote, China is strong in RF-SOI. RF-SOI will be growing at a CAGR of over 15% for the next five years, and China has production, design, wafer manufacturing and good momentum. “We will make a great contribution to the whole IC industry,” he predicted.
Of note, too, Russell Ellwanter, CEO of TowerJazz, gave what turned out to be a very inspirational keynote about Value Creation, and the importance of treating your suppliers with respect. He credits his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity. Five of their seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch.
Here are some more highlights from the day – but by all means check out the presentations for details. (You can click on the illustrations to see them in full screen.)
In her presentation, Embrace a Brand New Cooperation in 5G Era, Song asked where RF-SOI could help in her wish list. Could it increase integration and decrease cost and power consumption? Can it help improve NB-IoT device performance? The supply chain needs to come back around into a circle, so that the telcos are connected to and get insights from the wafer substrate providers, she said.
China Mobile has a 5G Innovation Center, and has established test labs in 8 cities. And the government has announced a 5G launch in 2020, with pre-commercial trials now going into 20 cities. So she was at the RF-SOI Workshop as much to listen and learn as to share China Mobile’s vision.
The presentation by Kidetoshi Kawasaki, GM of Sony Semiconductor Solutions, focused on antenna tuning, which he said is one of the fastest growing things in cell phones. Antenna Tuning Progress & SOI Single Chip Integration for 4G/5G UE (note that UE = user equipment) looks at antenna aggregation, and why it is important for carrier aggregation (CA) and MIMO. Sony has developed an SOI-based next-gen process for 5G integrating passive components. That’s why RF-SOI is important and will be continued to be used in the mobile market, he said.
GF has developed demo vehicles to help customers, said Sr. Director of the RF Business Unit, Peter Rabbeni. (Over the years they’ve shipped over 32 billion RF-SOI devices, btw.) In his presentation, RF-SOI: Delivering Performance & Integration for the Next Generation of Mobile,he noted that RF is becoming more complex than digital. As a result there is a need to integrate to help reduce cost: this is a direct correlation to the standards that are driving complexity. At the same time, performance requirements are increasing, so the challenge is driving increased performance at the same or lower cost than previous generations of products.
To meet 4G/LTE and 5G’s evolving performance demands, GF has recently introduced two new RF-SOI platforms, which he detailed in the presentation. 8SW enables increased integration of front-end modules (FEMs), while 45RFSOI is for mmWave FEMs. (In a separate presentation, IDDO-IC CEO Denis Masliah presented a Differential Complementary Millimeter Wave Power Amplifier for 5G using 45RFSOI process, which is currently being fabbed by GF.)
The two leading RF-SOI wafer suppliers, Soitec and partner Simgui, both gave excellent presentations. Though Soitec EVP Bernard Aspar’s presentation Engineered Substrates as Foundation of Innovation in RF is not posted, he made some important points. Up til now, RF-SOI has mainly been about switches and tuners, he said, but there are other opportunities that offer the potential for huge growth. The full supply chain needs to be prepared, he said, and suppliers need to understand each other. Each technology requires the right substrate – and even as we move into sub-6GHz 5G, there is still work to be done in 4G. In fact Soitec is now offering services to help customers better understand new substrate options.
Soitec’s partner in China, Simgui, now uses Soitec’s Smart CutTM technology for RF-SOI wafer production. Together the two are now producing over a million 200mm RF-SOI wafers/year, said Simgui Sr. Director, Kerui Wang. His presentation, RF-SOI – a Secured Substrate Supply Chain, looked at their strategic partnership with Soitec, wherein they use the same tools and processes to deliver the same products meeting the same specs.
Two leading fabless companies – RDA Microelectronics (which was acquired by Spreadtrum) and SmarterMicro also presented their RF-SOI activities. Although their ppts are not posted, here are a few highlights.
Longtime ASN readers will recall that RDA has been shipping high-volume, RF-SOI based chips to Samsung and others for over five years. In the presentation, RF-SOI in Current and Future RFFE Solutions, Engineering AVP Joseph Jia said that over last two years alone they’ve released almost 50 RFFE (front end) chips on RF-SOI. They see RF-SOI as the right match for switches, tuners and NB-IoT because of the low-voltage and tunability advantages.
SmarterMicro’s CTO, Peter Li, sees RF-SOI as a cornerstone of 5G. In his presentation, Reconfigurable RFFE in 5G, he said the goal is smart systems on fewer dies to decrease size and cost.
Jeff Zhu, assistant director at SMIC, presented SMIC, 0.13um RF-SOI Platform Updates. Mainland China’s largest foundry has recently moved its RF-SOI process from 180 to 130um, and he walked us through some chip designs.
Throughout the day, presenters noted that RF is a great opportunity for China to take a leadership position. As one panelist at the end of the day noted, RF depends more on expertise and talent than digital, which depends more on manpower.
Just before the Shanghai events, there was a 2-day event sponsored by the City of Nanjing, co-organized by SOI Industry Consortium and the City of Nanjing. Over 200 participants attended the workshop and tutorials on SOI applications, SoC development and manufacturing, EDA & IP ecosystem, as well as a design tutorial for More than Moore SOI ecosystem. Almost all of those presentations are now posted on the Consortium – click here to get them.
Some of the participants in the SOI Consortium’s delegation also had the opportunity to visit the enormous Nanjing Sofware Park. Nanjing, we learned, is often considered China’s “RF capital”. The list of the world’s major RF players working in partnership there is certainly an international who’s who.
So, lots of good RF-SOI/5G info on the SOI Consortium website – check it out!
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ASN asked Carlos Mazure and Giorgio Cesana, the Executive Directors of the SOI Consortium, to take a moment to share their outlook for 2018. Here’s what they had to say.
First of all, we’d like to wish everybody in the SOI ecosystem a safe, happy and prosperous 2018. We just finished up a great year, and now look forward to exciting prospects in the months to come.
Taking a quick look back, 2017 was marked by significant growth for RF-SOI markets, and with key product announcements for FD-SOI (accompanied by a very positive change in how it is viewed). In both domains, the foundries announced their roadmaps, so now the current sweet spots and future directions are clearly established.
Let’s take a moment to consider RF-SOI. As those following wireless markets know, RF-SOI has been the basis for antenna front-end modules in all the world’s smart phones for a few years now. With 2018, we see the industry turn its attention to 5G, with sub-6GHz in priority but also addressing the mmW space. Thanks to various flavors of RF-SOI, and RF integration in FD-SOI, we’ll move into a new phase where wireless will get faster and lower power than ever before.
This will be a hot topic in both the SOI Consortium symposiums around the world this year, and in articles coming your way here in ASN.
Another hot topic will be exciting new products coming out on FD-SOI. Chip design and manufacturing is of course always a fairly long process, and we’ve talked about the importance of building the ecosystem over the last few years. Now, a good ecosystem is in place. The design tools are ready and validated at the fabs, and key IP is ready. Of course with time there will be more and more IP, but lack of IP is no longer a barrier to design starts. Embedded memory – eMRAM – is another subject that designers want to learn more about, so that will be part of what we’ll be covering.
Last year we saw a growing list of successful FD-SOI tape-outs. In 2018, these chips will be ramping in volume. So this year, we look at products.
We’ll be inviting those companies that are ramping in silicon to present their chips at the various symposia we organize around the world: Silicon Valley in the spring, Tokyo in the summer, China in the fall.
Our symposia will again be accompanied by tutorial days, which have been very popular and successful. In this year’s tutorials there will be a particular focus on RF, analog and mixed-signal design, and they’ll dive deeper into how to use back biasing techniques for further boosting performance and lowering power.
So we’re at the beginning of what should be a very exciting year. We’d like to take a moment to thank all the member companies in the SOI Consortium for their enthusiastic support. And we look forward to welcoming new members over the course of this year.
With warm regards,
Giorgio Cesana and Carlos Mazure
Executive Directors of the SOI Consortium
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.
Day 2 of the recent SOI Workshop in Tokyo was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.
It was a really full day, so the recap in this post covers about half of the Day 2 presentations. My next post will cover the rest of them. (In case you missed it, Day 1 was covered in my previous post – you can read it here.)
Another Sony GPS Win!
The day kicked off with a talk by Sony GM Kenichi Nakano, entitled Sony Semiconductor Low-Power IoT Solution. He reminded the audience that Sony started looking at FD-SOI in 2013, and announced at ISSCC last year (the paper’s available from the IEEE – click here). Power, he said, is everything.
And that low-power GPS in Casio’s latest Pro Trek Smart watch, the WSD-F20? It’s based on Sony’s new CXD5602 – and that’s on FD-SOI, to which they give largely give credit for the >75% reduction in power from the previous generation.
Samsung: Surf’s Up!
FD-SOI is mature, and they’re ready to surf it, said Principle Designer at Samsung Foundry Marketing, Yongjoo Jeon. But, he added, they’ll continue to evolve it.
Covering a wide range of applications, he sees FD-SOI as a key in the 4th industrial revolution. In terms of power/performance, the “…excellent short channel effect enables better performance and lower power than bulk technology.” And, “Body bias enhances further performance [FBB – forward body bias] and power reduction [RBB – reverse body bias].”
That provides some unique benefits, he pointed out.
in automotive, it’s safety: the physical dielectric isolation is almost free from SER (soft error rate)
for analog/RF, the long channel gain is more significant with excellent noise immunity
for every application, lower doping enhances variation immunity
Samsung reached high yield (defect density D0<0.2) very quickly, and ramped rapidly to mass production (which is where they are with NXP as of Q1/17). This, he said, shows the maturity of their 28FDS FD-SOI technology.
Then he turned to design. Samsung (which does btw, offer Design Services) has an IP portfolio that is wide and deep, with a strong, well-established reference flow, supported by both Cadence and Synopsys.
In terms of RF, 28FDS has better fT than 28nm bulk. The physical isolation of the SOI structures enables a “no guard ring” approach, and specific RF offerings include LDMOS for PAs (power amplifiers). Samsung is supporting a new mm-Wave Pcell, which will be added in the V1.1 PDK.
Samsung is also adding eMRAM (embedded magnetoresistive RAM – it’s already yielding at 60%), as they see 28nm is probably the last node for eflash. “We’re very proud of these technologies,” he said.
Samsung’s next generation of FD-SOI will be 18nm, which provides a 20% increase in performance, a 40% decrease in power, and a 30% reduction in logic area.
Cadence EDA & IP Update
FD-SOI enablement usually means PDKs and tech files, noted Jonathon Smith, Director of Strategic Alliances at Cadence. But for deep benefits, you need to work with the foundries on characterizing libraries, and that’s just what Cadence is doing with both Samsung and GlobalFoundries, he said.
He gave a very frank and interesting talk entitled Enabling an Interconnected Digital World: Cadence EDA & IP Update. IoT, he noted, will include a lot of mixed-signal and complex packaging. Customers need modular reference flows, and they want flexibility and multiple foundry nodes. For FD-SOI, Cadence has been working on PDK enablement, tool readiness and design tools for several years. There is one database for both digital and analog.
For Samsung’s 28FDS, everything from logic synthesis to sign-off and analog tools are certified. In fact Cadence recently announced its custom/analog tools and full-flow digital and signoff tools have achieved Samsung certification for the PDK and foundation library (see the press release here).
For GlobalFoundries 22FDX, Cadence is certified across the entire design flow, and the reference flows are downloadable.
In terms of IP, he acknowledged that what Cadence has is not very extensive, so they are working with both partners and competitors. However, he did point out that their Tensilica IP for automotive is gaining traction: it is used in the Dreamchip ADAS chip fabbed on GF’s 22FDX, for example.
Wait, There’s More!
Day 2 in Tokyo was really packed with excellent presentations – too much for just one post. See Part 2 of my Day 2 coverage for highlights from Leti, GlobalFoundries, Soitec, MIPS/Imagination and more.
The FD-SOI ecosystem is strong. This was made clear at the recent Tokyo SOI Workshop, organized by the SOI Consortium. The event was spread out over two days, and most of the presentations are now posted (click here to access them). To cover the full scope of the workshop will take (at least) a couple ASN posts. So let’s start with Day 1, which was billed as the “FD-SOI Ecosystem” day.
It kicked off with a full-house for an afternoon session in the Yokohama Landmark Tower hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem.
David Sutton, CEO of EDA provider Silvaco opened the session with his talk, TCAD, EDA & IP to Support FD-SOI. Silvaco has deep FD-SOI roots, having supported Lapis Semi (formerly Oki) in its first forays into the technology – and that was back in 2002! The company is on a growth run this year, having acquired four companies, including IPextreme.
FD-SOI, he said, has been shown to be cost-effective. The capacity is in place, and it’s getting design wins. Silvaco’s full suite of EDA and custom CAD tools for FD-SOI cover the complete design flow from TCAD to sign-off. Their IP is very strong, he said, especially in automotive (including CAN IP), and their partnerships with key players like IBM and NXP are long running. In fact, Silvaco commercializes IP from NXP and others.
We got some great insights from Gregg Bartlett, GlobalFoundries’ SVP of the CMOS Business Unit, in his presentation FDX (FDSOI) Goes Mainstream – Roadmap for Product Competitiveness (it’s posted – click here to download it). “It is primetime for FD-SOI,” he said, and since one technology does not fit all, they’re redefining the mainstream. GF’s first FD-SOI offering, 22FDX, was qualified in March, and 12FDX will be taping out in the second half of 2018. They’ve currently got over 80 active engagements.
FD-SOI will be strong in China, he said. GF and the Chengdu municipality recently announced they are investing more than $100 million to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. This will lower the barriers to entry and increase IP availability even further, he said. They’re looking to put 500 design engineers in place. Customer tape-outs of 22FDX will begin at the new fab there in 2H2018, with volume production expected to start in 2019.
He went on to drill down on FDX applications, focusing on four main areas:
mobility: application processors that need high performance, RF integration and significant power reduction
IoT: this was the target when FDX was first conceived, and it continues to be a point of significant investment by the company
RF and mmWave: for BLE (Bluetooth Low Energy), WiFi, ZigBee and integrated PA’s (aka power amplifiers – where they’re seeing some impressive numbers, he said)
automotive: Grade 2 is done, and Grade 1 is underway (these are industry ratings related to reliability at the high-temperatures you get under the hood and in hotspots in the passenger compartment).
Citing a slide of customer testimonials, he concluded that the ecosystem is really starting to work, adding that they’ve got the right technology for the right applications, and it’s the right path for them to be on.
Invecas has been working on 22FDX since 2015 through a strategic partnership with GF. They’ve optimized IP and offer ASIC services, explained Bhaskar Kolla, the company’s Sr. Director of BizDev & Customer Engineering. His presentation, Invecas IP Portfolio in 22FDX is posted – click here to get it. It’s full of detail (standard cells, memories, analog & IO, and interface), so you’ll really want to check it out. The IPs are silicon proven and validated; the results are available, he said.
The foundation IPs are sponsored by GF, so they’re free to customers and cover a broad array of calibrations. They include forward and reverse body biasing (FBB and RBB) and body bias generator IP. Customers are really taking advantage of this, he said, citing as an example one that’s going for 2.5GHz by leveraging FBB.
Custom IP for analog & IO is a place they’re seeing a lot of interest, he continued, and on which they’re doing more and more work with clients. And their Interface IP is in a lot of silicon, especially for customers that are area sensitive. In fact, they’ve developed their own Interface IP demo platform in-house, from build through test and compliance checks.
In moving to FD-SOI, customers are seeing significant PPA improvements, he said. In one of the customer use cases for a high-level IoT product he cited, the customer requirements were easily achieved: cutting leakage in half, dynamic power consumption by roughly a third and area by 20%.
There’s so much technical detail on performance boosters in Laurent Grenouillet’s presentation, FD-SOI: a Low Power, High Performance Technology Scalable Down to 10nm, you really just have to look at it yourself – click here to get it. A CMOS & Memory Integration Expert at Leti, he did a quick review of 28-22-14nm, then took a deep dive into the myriad of performance boosting options for 10nm, including impressive benchmarking regarding the effectiveness of mobility boosters on FD-SOI vs. FinFET.
Here are the boosters he detailed for 28-22-14nm:
Interestingly he noted that with each node, the thickness of the insulating BOX layer of the SOI wafer scales down, and as it does, back bias efficiency improves even more.
Here’s what he then covered for 10nm (and detailed with data packed in the 20 slides that followed):
FD-SOI is the sweet spot when you need lower power, lower cost, more sensing (analog), more comm (RF), more flexibility and more energy efficiency, he concluded – and he provided powerful data to back that up.
I-fuseTM: the best OTP of Choice for FD-SOI and sub-14nm nodes was the topic of a talk by Attopsemi Technology’s Chairman, Shine Chung (you can get the ppt here). The company recently joined GF’s FDXcelerator partner program. OTP stands for one-time programmable memory, and I-fuse is different from other OTP technologies (notably NVM and e-fuses), he explained, in that it’s a non-breaking fuse with ultra-high reliability even in high-temp conditions. It’s been qualified by companies worldwide and is in volume production.
He’s a big fan of FD-SOI because it offers the best RF integration, small form factor, ULP and low cost. Want to make a cellphone as small as a watch? Then you need FD-SOI, he quipped with a tip of the hat to a Dick Tracy image. The fact that FD-SOI has a lower junction breakdown than bulk makes I-fuse the best choice for it, he said. You just program a gate as a fuse.
During breaks (on both days!), everybody was talking about the terrific Product Design Methodology presentation by Christophe Tretz, the SOI Consortium’s design guru (and longtime IBM guy). In fact, Christophe has agreed to write it up for ASN in the weeks to come, so don’t miss that. You’ll want to look at the whole presentation — click here to get it. In the meantime, here are some highlights.
He suggests designers consider an incremental approach in which FD-SOI benefits accrue. “No, you don’t have to know everything about the technology to use it,” he began (especially addressing those in smaller design teams and houses). “The ecosystem is there. Everything you need to use it is there.”
He used a number of cases to explain.
Case 1: a simple, digital SOC – you get significant power savings just by reusing existing library blocks and doing minor recompile.
Case 2: RF/mixed-signal – turnaround time is very fast (Analog Bits, for example cut leakage by 5x in a port that took just three months). FD-SOI gives analog designers a great new thing to play with for big power savings – and they learn fast.
Case 3 (= Cases 1 + 2): “complex” SOC with RF blocks – rework the RF blocks, but reuse library elements for the digital part without a lot of design effort. You get significant power savings very easily.
Case 4: a more complex SOC – in this case, you optimize or customize a few blocks in the first design pass, but then optimize/customize more blocks in subsequent design passes. It just keeps getting better and better.
Case X: a fully optimized SOC. This takes more time, but you can do parts in parallel and get dramatic results – especially if you use body biasing.
He then looked at the state of the ecosystem:
three fabs are ready
we have the tools (Synopsys, Cadence, Silvaco)
the libraries are there and ready to use
“You don’t have to learn everything to get your product out the door,” he concluded. “You don’t have to do it all at once: you can do it incrementally. Within a few months, you’ll have a nice product, and as you do new products every six months, each time you can re-use, but also tune for more improvements.”
In short: just do it!
So that’s a recap of Day 1. Next post (or posts?) I’ll recap Day 2. Stay tuned!
Over a hundred chip designers packed the room for the SOI Consortium’s recent FD-SOI Design Techniques Tutorial Day. Five professors and scientists from top institutions covered design techniques with real examples in digital, mixed-signal, analog, RF, mmW and ULV memory.
Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”
Many of the questions pertained to body biasing, which prompted STMicroelectronics Fellow and Professor Andreia Cathelin to state what may well have been the take-away of the day. “Body biasing is not an obligation,” she said. “It’s an opportunity.”
The tutorial, sponsored by both Samsung and GlobalFoundries, was hosted by Samsung at their San Jose headquarters. But as this was a paying event, the presentations are only available to those who attended. Having had the good fortune to attend, I can give you a quick recap of some of the highlights.
Professor Cathelin set the stage with a basic overview of FD-SOI design for analog, mixed-signal and mmW.
FD-SOI is a perfect match for the many up and coming SOCs that are often half analog and/or RF and mmW. She explained how FD-SOI makes the analog designer’s life much easier (no small feat, since analog can seem rather like blackbox magic to those on the digital side). FD-SOI improves: performance (even at high frequencies), noise, short device efficiency and brings in a new very efficient transistor knob through the Vt (threshold voltage) tuning range. She also explained and gave numerous real examples implemented in ST’s 28FDSOI on how:
For mmW design, the transistor should operate at Lmin, and hence you get excellence performance in terms of both transition frequency (Ft – set by the technology node) and maximum frequency (Fmax – what the designer can really get in the gain vs. speed trade-off). This can be conjugated with the fact that the back-end of line, despite the very fine nm node, takes advantage of the SOI features and brings in very decent quality factors.
For mixed-signal/high-speed design, she showed how and why FD-SOI gives you improved variability, a fantastic switch performance, and reduced parasitic capacitance. All these permit state of the art results in high-speed data converters, or, for example, lower frequency implementations which do not need any specific calibration for best in class linearity and ENOB (effective number of bits).
She also presented details on the CEA-Leti electrical models which are now the reference stand point (Leti-UTSOI2) for any FDSOI technology, and are implemented in several industrial Design Kits such those from ST.
Next on tap was a very lively talk with almost 60 slides by Professor Sorin Voinigescu of U. Toronto. He focused on how to use the main features of FD-SOI for efficient design of RF, mm-wave and broadband fiber-optic SOCs. We’re talking high-speed/high-frequency here, and he had real examples of chips fabbed in ST’s 28FDSOI and some simulated in GlobalFoundries’ 22FDX technology.
He examined layout issues and gave measurement tips and tricks, noting that there are a lot of things you can do in FD-SOI that you can’t do in bulk. It’s also easier to get high linearity in FD-SOI – yet another reason that he really likes it. Plus he sees it as competitive in terms of scaling even past 7nm.
Professor Joachim Rodrigues of Lund University in Sweden (the largest university in Scandinavia) talked about Design Strategies for ULV memories in 28nm FD-SOI (ST’s FD-SOI technology). Noting that SRAMs eat a lot of area in an SOC, he first proposed a standard cell-based memory (SCM) in 28nm FD-SOI that cut memory area by 35% and reduced leakage by 70%.
He then talked about other chips he and his team have presented at the world’s top chip conferences, including an ultra-low voltage (ULV) SRAM. For that chip they lay claim to having the best write performance in ULV in sub-65nm (15MHz at 240mV), and the best performing read capability across all technologies (30MHz at 240mV). In each case, he explained the fundamental design considerations, concepts and trade-offs.
Professor Borivoje “Bora” Nikolic of UC Berkeley is an expert in body-biasing for digital logic. He and his team have designed ten chips in ST’s 28nm FD-SOI, and they’re now working on their 8th generation of energy-efficient SOCs. During his 90-slide (!) tutorial, Energy-Efficient Processors in 28nm FDSOI, he covered: digital logic (including implementation and adaptive tuning of cores for optimal energy efficiency); SRAM and caches (design scenarios and results compared to bulk); supply (generating, switching and analog assists); back bias (how it’s generated and how to use it). He finished with (60 slides of!) design examples and the results they got for power (including adaptive voltage scaling) and performance. He said to be on the lookout for upcoming publications on (even more!) chips, as well as new work on 22nm designs.
Even if you don’t know anything about mixed-signal design, you can walk away from an hour-long lecture by Professor Boris Murmann of Stanford with a good understanding of what it’s all about. In his talk, Pushing the Envelope in Mixed-Signal Design Using FD-SOI, he explained how a mixed-signal person thinks about FD-SOI, and how the different metrics and sweetspots vary depending on what you’re working on. From there it was the deep dive, as he got into the heart of his talk: simulated transition frequency vs. gm/lD. He explained that while some things might seem counter intuitive (like long channels are more efficient for very low Ft requirements), it’s all related to electrostatics. It’s not yet well explained in the literature, he said, but it should be a big deal. And he explained why with FD-SOI, you don’t have to design for the worst case. He then talked about where he sees things going – he sees a very bright future indeed for FD-SOI and analog as computing moves into very low-power neural networks. In the end, he said, it all boils down to the FD-SOI performance benefits with respect to better gate control. This translates into “significant improvements” for many mixed-signal/RF building blocks.
All in all, it was a really terrific day. BTW, this tutorial day followed a full-day FD-SOI Symposium in Silicon Valley. Click here to read about that.
Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.
This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.) You’ll find the full program here. A brief summary follows.
The first day – Wednesday, May 31st – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.
It will take place on the 25th floor of the Yokohama Landmark Tower. The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.
The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.
It kicks off with talks on ultra-low power applications from Sony IoT and Samsung. Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure. The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.
Coffee breaks and lunch will give attendees and speakers time for further discussion.
This is a great opportunity – don’t miss it!