Tag Archive SOTB

Renesas’ New FD-SOI (SOTB) MCU for Energy Harvesting Applications (eenews)

Renesas, one of the world’s very top MCU manufacturers, is heralding its new FD-SOI based R7F0E017 for energy harvesting applications. In an in-depth article in the May 2019 edition of EENews Embedded, Renesas Product Marketing Manager Graeme Clark detailed the new chip, which is sampling this year. It’s a fascinating read, with lots of explanations about how SOI enables the cutting-edge features (like an integrated energy harvesting controller) – you won’t want to miss it.

BTW, here at ASN we’ve been covering the origins of this technology since 2005.They call it SOTB, for Silicon On Thin Box, but it is indeed their flavor of FD-SOI. The work started at Hitachi in cooperation with Renesas with a paper that debuted at IEDM 2004, then moved along through the series of mergers that resulted in the offering at what is Renesas Electronics today.

Here are some key quotes from the article:

The new SOTB process can now offer active mode current of less than 20 µA/MHz and leakage currents down to 150 nA, while still allowing the development of devices with reasonably high clock rates, large embedded flash memories and SRAMs on chip. This combination of integration and power consumption will make devices developed on this process ideal for energy harvesting applications. The result of this new process is that we can develop a new generation of microcontroller products.”

The use of the Silicon on Thin Buried Oxide technology on this new device has resulted in some unique low power characteristics. The first device has the following features and future devices using this process could offer even lower power consumption.

  • Active current of 20 µA /MHz
  • Standby Current of 200 nA
  • ADC operation 3 µA @ 32 kHz
  • 256 Kbyte SRAM with 1 nA / Kbyte standby current”

The R7F0E017 is able to run safely from a pure energy harvesting power source due to the operation of the Energy Harvesting Controller. The device can operate from a wide range of potential energy sources including solar power, vibration, pressure and temperature difference, and many others. The integrated energy harvesting controller, supported by very few inexpensive external components, completely manages the cyclic wake-up sequence of the microcontroller, only using the extremely low energy harvesting source current.”

Click here to read the full article on the eenewseurope website.

Renesas Coming Out with 65nm FD-SOI chips (but they call it SOTB), says EETimes Japan

Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.

If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.

Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.

We learned all this and much more during the very successful 2014 IEEE S3S Conference.

The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.

 S3S14banner

 

Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.

(Photo credit: Justin Lloyd)

S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)

 The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.

 The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.

 

Sub-Threshold Microelectronics

The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.

3D Integration

The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).

Key Fully-Depleted SOI Technical results

Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.

STMicroelectronics and CEA-Leti gave us a wealth of information on:

  • From "Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology" in the S3S '14 "Energy Efficiency" short course by P. Flatresse (Source: STMicroelectronics)

    From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)

    How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).

  •  How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).

The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).

In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.

More than An Order of Magnitude Energy Improvement of

From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)

The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.

On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

FinFET_SOI_IBM_S3S14_Mobility_1

Join the conference in 2015!

Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.

The organizing committee is looking forward to seeing you there!

~~~

 

Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory.  He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT.  Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices.  Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.

Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors.  He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999.  As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials.  As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes.  He has authored or co-authored over 50 papers and holds over 10 patents.

 

 

*RO = ring oscillator

 

 

The SOI Papers at VLSI ’14 (Part 2):

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!

 

(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.

 

4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.

 

6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.

 

8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalon et al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.

 

9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.

 

13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

 

13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

 

17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

 

18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.

 

18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.

 

18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.

 

SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.

 

UTwenteC194VLSI14lowres

(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)

 

 

C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14).

By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions.

Here’s a quick preview.

Papers in the Jumbo-Joint Focus Sessions

JJ2-3: FDSOI Process/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs, R. Ranica et al., STMicroelectronics & CEA-LETI

In this paper from STMicroelectronics and CEA-LETI, six Transistor SRAM (6T- SRAM) cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage (0.197µm2) purposes are fabricated with 28 nm node FDSOI technology for the first time. Starting from a direct porting of bulk planar CMOS design, the improvement in read current Iread has been confirmed up to +50% (@Vdd=1.0V) & +200% (@ Vdd=0.6 V), respectively, compared with 28 nm Low-Power (LP) CMOS technology. Additionally, -100mV minimum operating voltage (Vmin) reduction has been demonstrated with 28 nm FDSOI technology. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197µm2 . Ultimate stand-by leakage below 1pA on 0.120 µm2 bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

Cross-sectional and plain view of FDSOI SRAM cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage(0.197µm2).

JJ1-8: First Demonstration of a Full 28nm High-k/Metal Gate Circuit Transfer from Bulk to UTBB FDSOI Technology Through Hybrid Integration, D. Golanski et al, ST Microelectronics and CEA-LETI

For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame of our hybrid technology. Competitive ESD performance for the same footprint is achieved through hybrid MOSFETS snap-back voltage reduction, obtained by implant engineering. In addition, we demonstrate that the performance of Silicon Controlled Rectifier (SCR) and ESD diodes are matched vs Bulk technology while maintaining the performance of FDSOI devices and without any additional masks.

JJ1-9: 2.6GHz Ultra-Wide Voltage Range Energy Efficient Dual A9 in 28nm UTBB FD-SOI, D. Jacquet et al. STMicroelectronics

This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to 1.2V, and forward body bias (FBB) techniques up to 1.3V bias voltage, thus enabling an extremely energy efficient implementation.
(Note: ST has indicated that 2.6GHz voltage range in the title dates from the time the paper was submitted earlier this year; the actual presentation will show a more extended range.)

JJ2-1 (Invited): Fully-Depleted Planar Technologies and Static RAM, T. Hook et al, IBM, STMicroelectronics, LETI

Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described.Thick- and thin-Bottom Oxide (BOX) variants are discussed.

JJ2-4: Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Y. Yamamoto et al, Low-power Electronics Association & Project (LEAP), The University of Tokyo

We demonstrated record 0.37 V minimum operation voltage (Vmin) of 2Mbit Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to small variability of SOTB (AVT~1.2-1.3 mVμm) and adaptive body biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
(Note: SOTB is a flavor of planar FD-SOI.)

In the Circuits Symposia

Paper T2-2: High Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant- Free Process and Aggressively-Scaled Fin and Gate Dimensions, P. Hasemi et al., IBM & GlobalFoundries.

The adoption of advanced high-mobility Silicon Germanium (SiGe) channel materials with aggressively scaled Tri-gate pFETs on insulator is reported for the first time. SiGe is widely known as a suitable channel material for p-type MOS device, thanks to its higher hole mobility than that in conventional silicon material. In this paper, IBM and GlobalFoundries report a SiGe channel Tri-gate pFET with aggressively scaled Fin width (Wfin) and Gate length(Lg) dimensions, which is fabricated using SiGe on insulator substrate. Excellent electrostatic control down to Lg= 18 nm and Wfin< 18 nm has been reported. Using an optimized implant-free raised source/drain process, on-current Ion = 1.1 mA/µm at off-leakage current Ioff = 100 nA/µm and supply voltage Vdd= 1.0 V has been achieved.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm. (b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm.
(b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

15-4: A 28GHz Hybrid PLL in 32nm SOI CMOS, M. Ferriss et al, IBM

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140μmx160μm 32μm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.

21-1: A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS, L. Kull et al, IBM, EPFL

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time skew minimization and per-channel gain control based on low-power reference voltage buffers. Gain control of each sub-ADC is based on a fine-grain, robust R-3R ladder. The sub-ADC stacks the capacitive SAR DAC with the reference capacitor to reduce the area and enhance the settling speed. The speed and area optimized sub-ADC as well as a short tracking window of 1/8 period enable a low input capacitance and therefore render an input buffer unnecessary. The ADC achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2in 32nm CMOS SOI technology.

21-3: An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI, V.H.-C. Chen and L. Pileggi, Carnegie Mellon University

This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.

In the Technology Symposia

5-3: Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS, Z. Yuan et al, Stanford University, Applied Materials, Sematech, Texas State University

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional FinFETs. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

10-1: Benefits of Segmented Si/SiGe p-Channel MOSFETs for Analog/RF Applications, N. Xu et al, University of California, Applied Materials, Soitec

Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.

14.5: 64nm Pitch Interconnects: Optimized for Designability, Manufacturability and Extendibility, C. Goldberg et al, STMicroelectronics, Samsung Electronics, GlobalFoundries, IBM

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been plugged in to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.

15-1: Innovative Through-Si 3D Lithography for Ultimate Self-Aligned Planar Double-Gate and Gate-All-Around Nanowire Transistors, R. Coquand et al, STMicroelectronics, CEA-LETI, IMEP-LAHC

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2-Poly-Si gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION of 1mA per μm at VT+0.7V) with excellent electrostatics (SS down to 62mV per dec and DIBL below 10mV per V at LG 80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of lowpower SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.

15-3: Scaling of Ω-Gate SOI Nanowire N- and P-FET Down to 10nm Gate Length: Size- and Orientation-Dependent Strain Effects, S. Barraud et al, CEA-LETI, CEA-INAC, STMicroelectronics, IMEP-LAHC

High-performance strained Silicon-On-Insulator nanowires with gate width and length scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ etching and selective epitaxial growth of boron-doped SiGe for the formation of recessed Sources/ Drains (S/D). We show an ION improvement up to +100% induced by recessed SiGe S/D for LG=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <110> Si NWs provide the best opportunities for strain engineering.

17-2 (Late News): Experimental Analysis and Modeling of Self Heating Effect in Dielectric Isolated Planar and Fin Devices, S. Lee et al, IBM

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.

The Moment Is Now

There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes.

Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them.

The four most significant reasons to change to this solution now rather than later are that hybrid SOTB:

1. cuts power and leakage in half

2. gets threshold voltage (Vt) and variability under control

3. is fully compatible with current bulk design is easy to manufacture.

4. is easy to manufacture. Read More

Less Than Ever

Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation.

In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research Laboratory demonstrated that the planar FDSOI devices fabricated on SOTB have the smallest Vth variability among planar CMOS due to low-dose channel and back bias control. Read More