Tag Archive SRAM

What’s Behind the Power Savings in sureCore’s FD-SOI SRAM IP?

By Duncan Bremner, CTO SureCore Limited

Editor’s note: sureCore just announced availability of its 28nm FD-SOI memory compiler (press release here), which supports the company’s low-power, Single and Dual Port SRAM IP. Here, the company’s CTO explains why this IP is getting such impressive results.

~ ~ ~

Recently, sureCore announced results from a 28nm FD-SOI test chip that showed dynamic power savings exceeding 75% and static power cuts up to 35% (when compared against a number of current commercial offerings), while only incurring a 5-10% area penalty for its ultra-low power SRAM IP.

And while this data is easily substantiated as shown in Figure 1, the sceptical industry pundits have raised questions that fall into two camps: (a) That can’t be done; or (b) How did they manage that? In answer to both of these questions, here’s a quick look at the history and engineering strategy that we adopted to deliver these results.

sureCore_FDSOI_power_comparison2

Figure 1: sureCore SRAM performance versus 5 leading IP suppliers.

Looking back to the early days of sureCore, SRAM fascinated us because despite many process iterations, the SRAM in use today bears a striking resemblance to the SRAM architectures that existed in the ’70s and ’80s. We concluded that no one had really taken a “blank-sheet-of-paper” look at the architecture for over 40 years. Recognising the growing importance of power efficiency for SoCs targeting forward-looking applications such as wearables, IoT, and other mobile devices, we examined power consumption in detail, and began by investigating how we could reduce SRAM power to a level attractive to the next generation of power critical, SoC designers.

Our starting point differed significantly from the traditional approach to SRAM R&D that typically starts at the bit cell. We recognised that the basic bit cell is fixed by the foundry; it’s a piece of electronics that is carefully optimised for fabrication. Modern bit cells are designed by the foundries who tend to put an emphasis on the broadest possible manufacturability drivers; yield and faster-time-to-volume as opposed to more performance-centric metrics. Their focus is on the front-end process optimisation, area and yield.

The basic rule of R&D fabless foundry engagement has been, “use the storage array – you won’t get a better packing density.” Consequently, the application use model had become separated from the technology — ‘faster or cheaper’ became the industry’s mantra instead of ‘faster and better’. This resulted in SRAM design teams focusing on how to build more sensitive read amplifiers to detect the signals, and better write amplifiers to drive the signal on to the bit cell. Not much time was spent looking at the fundamental architecture and asking: “Is this the best way?”

sureCore decided to take a more holistic view and stood back from the whole problem. We started with a clean sheet of paper and asked, “Where does the power go when you start storing data on SRAM?”

We discovered that a lot of the power is consumed hauling parasitic capacitance around. Our design strategy was therefore very simple; we developed a system architecture to optimize power while still retaining the area advantages of the standard foundry bit cell.

Simply stated, we architected the internal block architecture of SRAM by splitting the read amplifier function into a local and global read amplifier, thus dividing the capacitive load from the word-line, only driving the areas being addressed and not the whole array. This resulted in significant dynamic power savings during the read cycle. In a similar fashion, we reduced the write cycle power by a similar amount. Whilst hierarchical solutions are not new, the sureCore “secret sauce” is at circuit level developed by our engineering teams leading to not only significant power savings, but also comparable performance levels.

Our “blank sheet” approach delved deep; right down to the fundamental device physics level. Our strategic partners, Gold Standard Simulations — recognised world leaders in modelling devices at the atomic level and experts in nano-scale process nodes, helped us to understand the behaviour and limitations of processes at nodes below 28nm at a device level and bit cell level. Combining this fundamental device understanding with excellent circuit design and system analysis skills, we’ve identified where existing SRAM solutions waste power, and architected our solution to avoid this; we deliver power savings without the added complexity of write and read-assist.

At the outset, we determined it was important that our IP be process-independent. sureCore IP is based on architecture and circuit techniques rather than a reliance on process features. The result of this is technology that can reduce power in standard bulk CMOS, but is equally applicable to newer FinFET or FD-SOI processes and across all geometries, even down to 16nm and below. We believe our approach is paying off and, because we insisted in retaining the foundry optimised bit cell, sureCore’s technology can be retrofitted into existing designs enabling extended product life cycles.

This is our basic technology story… a start-up deciding to take a fresh look at an old technology and dramatically improving power performance over 75% compared with existing solutions. This is a new approach to SRAM power consumption for power sensitive applications and it delivers tangible battery life benefits to both the end user and the FD-SOI designers. Today’s FD-SOI technology is optimised for low power applications, bringing extended battery life to the nascent markets of wearables and IoT.

IBM 0.3V SOI-FinFET SRAM paper garners press attention

An IBM paper on a 14nm SOI-FinFET SRAM functional down to 0.3V has garnered press attention. The paper, entitled 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation by R.V. Joshi et al, was presented during the Symposium on VLSI Circuits in Kyoto, Japan in June. According to the abstract, the authors presented a new, “… dynamic supply and interconnect boosting techniques for low voltage SRAMs and logic in deep 14nm FinFET technologies. The capacitive coupling in a FinFET device is used to dynamically boost the virtual logic and array supply voltage, improving Vmin. Hardware measurements show a 2.5-3x access time improvement at lower voltages and a functional Vmin down to 0.3V. Results are supported by novel physics-based capacitance extraction and novel superfast statistical circuit simulations.” EETimes reported on the paper in a piece entitled “IBM Slashes Next-Gen Power” (see it here), wherein the lead author confirmed that this work was based on a 14nm SOI-FinFET architecture.

On FD-SOI, Surecore’s ULP SRAM Saves 70% Power; Company Raised $1.6 Million (SemiEngineering)

SureCore’s ultra-low power SRAM technology on 28nm FD-SOI saves 70% in read/write power and reduces leakage by 30% compared to 40nm bulk implementations, writes SemiconductorEngineering Editor-In-Chief Ed Sperling (read the article here). Hitting the sweet spot for mobile, IoT and wearables, SureCore recently raised $1.6 million in funding.

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices.

Brief summaries, culled from the program (and some of the actual papers) follow.

 

SOI-FinFETS

9.4 2nd Generation Dual-Channel Optimization with cSiGe for 22nm HP Technology and Beyond (IBM)

This paper about performance boosters is applicable to all flavors of SOI-based devices, including FinFET, planar FD-SOI and partially-depleted SOI. At 22nm for high-performance (HP), IBM is still doing the traditional partially-depleted (PD) SOI. At 14nm, when they go to SOI-FinFETs, one of the channel stressors to boost performance is Silicon-Germanium (cSiGe). To better understand the physics, layout effects and impact of cSiGe on device performance, IBM leveraged their 22nm HP technology to do a comprehensive study. They got a 20% performance boost and 10% Short Channel Effect (SCE) improvement, and showed that this 2nd generation high-performance dual-channel process can be integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.

 

13.5 Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs  (GlobalFoundries, IBM)

SOI FINFETs are very attractive because of their added immunity to Vt variability due to undoped channels. However, circuit level performance also depends on the effective current (Ieff) variability. According to the advance program, “A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.”

 

20.5 Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs (AIST, Nissin Ion Equipment)

In this paper, the researchers thoroughly investigated the impact of the heated ion implantation (I/I) technology on HK/MG SOI FinFET performance and reliability, which it turns out is excellent. They demonstrated that “…the heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that the heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability, and bias temperature instability (BTI) for both nMOS and pMOS FinFETs in comparison with conventional room temperature I/I.”

 

26.2:  Advantage of (001)/<100> oriented Channel to Biaxial and Uniaxial Strained Ge-on-Insulator pMOSFETs with NiGe S/D (AIST)

In this paper about boosters in fully-depleted planar SOI and GeOI based devices, the researchers “compared current drivability between (001)/<100> and (001)/<110> strained Ge-on-insulator pMOSFETs under biaxial and uniaxial stress.” They experimentally demonstrated for the first time that in short channel (Lg < 100 nm) devices, <100> channels exhibit higher drive current than <110> channels under both the biaxial- and the uniaxial stress, in spite of the disadvantage in mobility, although this is not the case with longer channel devices. The advantage is attributable to higher drift velocity in high electric field along the direction and becomes more significant for shorter Lg devices. The strained-Ge (001)/<100> channel MOSFET have a potential to serve as pFET of ultimately scaled future CMOS.

 

33.1 Simulation Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability (Invited) (U. Glasgow, GSS, IBM)

With ever-reducing design cycles and time-to-market, design teams need early delivery of a reliable PDK before mature silicon data becomes available. This paper shows that the GSS ‘atomistic’ simulator GARAND used in this study provides accurate prediction of transistor characteristics, performance and variability at the early stages of new technology development and can serve as a reliable source for PDK development of emerging technologies, such as SOI FinFET.  Specifically, the authors report on, “…a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modeling strategy is developed for early delivery of a reliable PDK, which enables TCAD- based transistor-SRAM co-design and path finding for emerging technology nodes.” 

 

RF-SOI

1.3: Smart Mobile SoC Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities (Qualcomm)

In this plenary presentation, Geoffry Yeap, VP of Technology at Qualcomm gave a perspective on state of the art mobile SoCs and RF/analog technologies for RF SOCs. The challenge, he said in his paper, is “…lower power for days of active use”. He cited the backgate for asymmetric gate operation and dynamic Vt control, noting that FinFETs lack an easy way to access the back gates. “This is especially crucial when Vdd continues to scale lower to a point that there is just not sufficient (Vg-Vt) to yield meaningful drive current,” he continued. While he sees FD-SOI “very attractive”, he is concerned about the ecosystem, capacity and starting wafer price.

With respect to RF-SOI, the summary of his talk in the program stated, “Cost/power reduction and unique product capability are enabled by RF front end integration of power amplifiers, antenna switches/tuners and power envelope tracker through a cost-effective RF-SOI instead of the traditional GaAs.”

 

Advanced Devices

Post-FinFETs, one of the next-generation device architectures being heavily investigated now is  gate-all-around (GAA). While FinFETs have gate material on three sides, in GAA devices the gate completely surrounds the channel. A popular fabrication technique is to build them around a nanowire, often on an SOI substrate.

4.4 Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling  (Forschungszentrum Jülich, U. Udine, Soitec)

This is a paper about a strained Si (sSi) nanowire array Tunnel FETs (TFETs). The researchers demonstrated that scaled gate all around (GAA) strained Si (sSi) nanowire array (NW) Tunnel FETs (TFETs) allow steep slope switching with remarkable high ION due to optimized tunneling junctions. Very steep tunneling junctions have been achieved by implantations into silicide (IIS) and dopant segregation (DS) with epitaxial Ni(AlxSi1-x)2 source and drain. The low temperature and pulse measurements demonstrate steep slope TFETs with very high I60 as TAT is suppressed. GAA NW TFETs seem less vulnerable to trap assisted tunneling (TAT). Time response analysis of complementary-TFET inverters demonstrated experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

 

IBM_IEDMBangsaruntip20.2Fig.4

(image courtesy: IBM, IEEE/IEDM)

20.2 Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond (IBM)

Record Silicon Nanowire MOSFETs: IBM researchers described a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10-nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured an incredible 30-nm SiNW pitch (the spacing between adjacent nanowires) with a gate pitch of 60 nm. Devices with a 90-nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

 

 

26.4 FDSOI Nanowires: An Opportunity for Hybrid Circuit with Field Effect and Single Electron Transistors (Invited) (Leti)

This paper is about nanowires and single electron transistors (SET).  As indicated in the  program, “When FDSOI nanowires width is scaled down to 5nm, the nanowires can encounter a dramatic transition to single electron transistor characteristics. This enables the first room temperature demonstration of hybrid SET-FET circuits thus paving the way for new logic paradigms based on SETs. Further scaling would rely on deterministic dopant positioning. We have also shown that Si based electron pumps using tunable barriers based on FETs are promising candidates to realize the quantum definition of the Ampere.”

 

26.6 Asymmetrically Strained High Performance Germanium Gate-All-Around Nanowire p-FETs Featuring 3.5 nm Wire Width and Contractable Phase Change Liner Stressor (Ge2Sb2Te5) (National U. Singapore, Soitec)

In this paper about GAA and nanowires, the researchers report “…the first demonstration of germanium (Ge) GAA nanowire (NW) p-FETs integrated with a contractable liner stressor. High performance GAA NW p-FET featuring the smallest wire width WNW of ~3.5 nm was fabricated. Peak intrinsic Gm of 581 μS/μm and SS of 125 mV/dec was demonstrated. When the Ge NW p-FETs were integrated with the phase change material Ge2Sb2Te5 (GST) as a liner stressor, the high asymmetric strain was induced in the channel to boost the hole mobility, leading to ~95% intrinsic Gm,lin and ~34% Gm,sat enhancement. Strain and mobility simulations show good scalability of GST liner stressor and great potential for hole mobility enhancement.”

 

III-V, More Than Moore and Other Interesting Topics

28.5 More than Moore: III-V Devices and Si CMOS Get It Together (Invited) (Raytheon)

This is continuation of a major ongoing III-V and CMOS  integration project that Raytheon et al wrote about in ASN five years ago (see article here).  As noted in the IEDM program, the authors “…summarize results on the successful integration of III-V electronic devices with Si CMOS on a common silicon substrate using a fabrication process similar to SiGe BiCMOS. The heterogeneous integration of III-V devices with Si CMOS enables a new class of high performance, ‘digitally assisted’, mixed signal and RF ICs.

 

31.1 Technology Downscaling Worsening Radiation Effects in Bulk: SOI to the Rescue (Invited) (ST)

In this paper, the authors explore the reliability issues faced by the next generation of devices.  As they note in the description of the paper in the program, “Extrinsic atmospheric radiations are today as important to IC reliability as intrinsic failure modes. More and more industry segments are impacted. Sub-40nm downscaling has a profound impact on the Soft Error Rate (SER) of BULK technologies. The enhanced resilience of latest SOI technologies will fortunately help leveraging existing robust design solutions.”

 

13.3 A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications (ST, Luxtera)

Luxtera’s work on Silicon Photonics and now products based on integrated optical communications has been covered here at ASN for years. In this paper Luxtera and ST (which now is Luxtera’s manufacturing partner) present a low-cost 300mm Silicon Photonics platform for 25Gb/s application compatible with 3D integration and featuring competitive optical passive and active performance. This platform aims at industrialization and offering to system designers a wide choice of electronic IC, targeting markets applications in the field of Active optical cables, optical Modules, Backplanes and Silicon  Photonics Interposer.

 

Irisawa (2.2) Fig.9

The graph above shows the high electron mobility of Triangular MOSFETs with InGaAs Channels. (Image courtesy: AIST, IEEE/IEDM) 

 

2.2. High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures (AIST, Sumitomo, Tokyo Institute of Technology)

InGaAs is a promising channel material for high-performance, ultra-low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration. A research team led by Japan’s AIST built triangular InGaAs-on-insulator nMOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30 nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 μA/μm at a 300-nm gate length, showing they have great potential for ultra-low power and high performance CMOS applications.

 

16.4. High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator Tri-gate MOSFETs with high short channel effect immunity and Vth tenability (Sumitomo, Tokyo Institute of Technology)

This III-V paper investigates the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. “It was found that Tbody scaling provides better SCEs control, whereas Tbody scaling causes μfluctuation reduction. To achieve better SCEs control, Tchannel scaling is more favorable than Tbuffer scaling, indicating QW channel structure with MOS interface buffer is essential in InAs-OI MOSFETs. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/μm. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control. These results strongly suggest that the Tri-gate ETB III-V-OI structure is very promising scaled devices on the Si platform to simultaneously satisfy high performance high SCE immunity and Vth tunability.”

11.1 A Flexible Ultra-Thin-Body SOI Single-Photon Avalanche Diode (TU Delft)

This is a paper on flexible electronics for display and imaging systems. “The world’s first flexible ultra-thin-body SOI single-photon avalanche diode (SPAD) is reported by device layer transfer to plastic with peak PDP at 11%, DCR around 20kHz and negligible after pulsing and cross-talk. It compares favorably with CMOS SPADs while it can operate both in FSI and BSI with 10mm bend diameter,” say the researchers.

 

11.7 Local Transfer of Single-Crystalline Silicon (100) Layer by Meniscus Force and Its Application to High-Performance MOSFET Fabrication on Glass Substrate (Hiroshima U.)

In this is a paper on flexible electronics for display and imaging systems, the researchers “…propose a novel low-temperature local layer transfer technique using meniscus force. Local transfer of the thermally-oxidized SOI layer to glass was carried out without any problem. The n-channel MOSFET fabricated on glass using the SOI layer showed very high mobility of 742 cm2V-1s-1, low threshold voltage of 1.5 V.  These results suggest that the proposed (meniscus force-mediated layer transfer) technique (MLT) and MOSFET fabrication process opens up a new field of silicon applications that is independent of scaling.”

 

Note: the papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.

 

Special thanks to Mariam Sadaka and Bich-Yen Nguyen of Soitec for their help and guidance in compiling this post.

The IEEE S3S Conference Delivered Impressive Technical Content

Layout 1

EDS Logo PMS3015_revu

BayMonterey

A view of the Bay from Cannery row, Monterey, CA.

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.

The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).

Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.

IBM_GF_SOIFinFET

Chart from A. Paul (GF) showing benefits of Fin width scaling

The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)

 

 

The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.

sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).

An impressive hot topics session was dedicated to RF CMOS.

J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.

Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.

The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).

The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.

The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.

IBM3DI_S3S13ConfShortCourse

Snapshot from Dr M. Farooq’s (IBM) presentation (3DI shortcourse)

3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.

 

The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.

Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14).

By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions.

Here’s a quick preview.

Papers in the Jumbo-Joint Focus Sessions

JJ2-3: FDSOI Process/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs, R. Ranica et al., STMicroelectronics & CEA-LETI

In this paper from STMicroelectronics and CEA-LETI, six Transistor SRAM (6T- SRAM) cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage (0.197µm2) purposes are fabricated with 28 nm node FDSOI technology for the first time. Starting from a direct porting of bulk planar CMOS design, the improvement in read current Iread has been confirmed up to +50% (@Vdd=1.0V) & +200% (@ Vdd=0.6 V), respectively, compared with 28 nm Low-Power (LP) CMOS technology. Additionally, -100mV minimum operating voltage (Vmin) reduction has been demonstrated with 28 nm FDSOI technology. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197µm2 . Ultimate stand-by leakage below 1pA on 0.120 µm2 bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

Cross-sectional and plain view of FDSOI SRAM cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage(0.197µm2).

JJ1-8: First Demonstration of a Full 28nm High-k/Metal Gate Circuit Transfer from Bulk to UTBB FDSOI Technology Through Hybrid Integration, D. Golanski et al, ST Microelectronics and CEA-LETI

For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame of our hybrid technology. Competitive ESD performance for the same footprint is achieved through hybrid MOSFETS snap-back voltage reduction, obtained by implant engineering. In addition, we demonstrate that the performance of Silicon Controlled Rectifier (SCR) and ESD diodes are matched vs Bulk technology while maintaining the performance of FDSOI devices and without any additional masks.

JJ1-9: 2.6GHz Ultra-Wide Voltage Range Energy Efficient Dual A9 in 28nm UTBB FD-SOI, D. Jacquet et al. STMicroelectronics

This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to 1.2V, and forward body bias (FBB) techniques up to 1.3V bias voltage, thus enabling an extremely energy efficient implementation.
(Note: ST has indicated that 2.6GHz voltage range in the title dates from the time the paper was submitted earlier this year; the actual presentation will show a more extended range.)

JJ2-1 (Invited): Fully-Depleted Planar Technologies and Static RAM, T. Hook et al, IBM, STMicroelectronics, LETI

Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described.Thick- and thin-Bottom Oxide (BOX) variants are discussed.

JJ2-4: Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Y. Yamamoto et al, Low-power Electronics Association & Project (LEAP), The University of Tokyo

We demonstrated record 0.37 V minimum operation voltage (Vmin) of 2Mbit Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to small variability of SOTB (AVT~1.2-1.3 mVμm) and adaptive body biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
(Note: SOTB is a flavor of planar FD-SOI.)

In the Circuits Symposia

Paper T2-2: High Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant- Free Process and Aggressively-Scaled Fin and Gate Dimensions, P. Hasemi et al., IBM & GlobalFoundries.

The adoption of advanced high-mobility Silicon Germanium (SiGe) channel materials with aggressively scaled Tri-gate pFETs on insulator is reported for the first time. SiGe is widely known as a suitable channel material for p-type MOS device, thanks to its higher hole mobility than that in conventional silicon material. In this paper, IBM and GlobalFoundries report a SiGe channel Tri-gate pFET with aggressively scaled Fin width (Wfin) and Gate length(Lg) dimensions, which is fabricated using SiGe on insulator substrate. Excellent electrostatic control down to Lg= 18 nm and Wfin< 18 nm has been reported. Using an optimized implant-free raised source/drain process, on-current Ion = 1.1 mA/µm at off-leakage current Ioff = 100 nA/µm and supply voltage Vdd= 1.0 V has been achieved.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm. (b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm.
(b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

15-4: A 28GHz Hybrid PLL in 32nm SOI CMOS, M. Ferriss et al, IBM

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140μmx160μm 32μm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.

21-1: A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS, L. Kull et al, IBM, EPFL

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time skew minimization and per-channel gain control based on low-power reference voltage buffers. Gain control of each sub-ADC is based on a fine-grain, robust R-3R ladder. The sub-ADC stacks the capacitive SAR DAC with the reference capacitor to reduce the area and enhance the settling speed. The speed and area optimized sub-ADC as well as a short tracking window of 1/8 period enable a low input capacitance and therefore render an input buffer unnecessary. The ADC achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2in 32nm CMOS SOI technology.

21-3: An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI, V.H.-C. Chen and L. Pileggi, Carnegie Mellon University

This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.

In the Technology Symposia

5-3: Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS, Z. Yuan et al, Stanford University, Applied Materials, Sematech, Texas State University

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional FinFETs. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

10-1: Benefits of Segmented Si/SiGe p-Channel MOSFETs for Analog/RF Applications, N. Xu et al, University of California, Applied Materials, Soitec

Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.

14.5: 64nm Pitch Interconnects: Optimized for Designability, Manufacturability and Extendibility, C. Goldberg et al, STMicroelectronics, Samsung Electronics, GlobalFoundries, IBM

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been plugged in to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.

15-1: Innovative Through-Si 3D Lithography for Ultimate Self-Aligned Planar Double-Gate and Gate-All-Around Nanowire Transistors, R. Coquand et al, STMicroelectronics, CEA-LETI, IMEP-LAHC

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2-Poly-Si gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION of 1mA per μm at VT+0.7V) with excellent electrostatics (SS down to 62mV per dec and DIBL below 10mV per V at LG 80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of lowpower SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.

15-3: Scaling of Ω-Gate SOI Nanowire N- and P-FET Down to 10nm Gate Length: Size- and Orientation-Dependent Strain Effects, S. Barraud et al, CEA-LETI, CEA-INAC, STMicroelectronics, IMEP-LAHC

High-performance strained Silicon-On-Insulator nanowires with gate width and length scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ etching and selective epitaxial growth of boron-doped SiGe for the formation of recessed Sources/ Drains (S/D). We show an ION improvement up to +100% induced by recessed SiGe S/D for LG=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <110> Si NWs provide the best opportunities for strain engineering.

17-2 (Late News): Experimental Analysis and Modeling of Self Heating Effect in Dielectric Isolated Planar and Fin Devices, S. Lee et al, IBM

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART

Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).

Understanding SRAM sense amps in SOI design

As the SOI circuit switches, the body voltages of the switching transistors will change from their previous steady state condition. This is called the history effect. This is one of the most interesting circuit design issues in SOI but it is also a benefit of SOI that contributes to the SOI performance advantage over bulk CMOS. Leveraging tools to model and predict the body voltage of the SOI transistors will lead to a successful SOI circuit design. Read More

The right choice for 22nm SRAM

What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may trump performance for high-volume markets, however.

Our work recently presented at the 2009 IEEE SOI Conference indicates that a planar fully depleted (FD) structure on very thin-BOX (~10nm thick) is a compelling candidate. Specifically, we found that for 6T-SRAM cells at the 22nm node:

  • planar FD-SOI structures on thin-BOX are significantly better than planar bulk-Si structures, in terms of both performance and yield;
  • although planar FD-SOI structures on thin-BOX cannot yet match FinFETs in performance, their performance is adequate and they are easier to manufacture for high-volume applications demanding high yields.

Read More