Tag Archive ST


The Promise of High Resistivity SOI for Wireless Communications Systems

ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.

Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.

A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) ( 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications Read More


A GaN Approach to Schottky Diodes

The G²REC program aims to create a new generation of energy-efficient power devices for high-volume applications over 250V.

The greater electronics industry has an urgent need for fast-switching, high-voltage, energy-efficient and cost-competitive rectifiers.

Rectifiers (which convert AC to DC) are comprised of diodes, components that ensure electricity flows in just one direction. For certain high-volume applications such as power factor correction (PFC) in computer server power supplies and motor control in large appliances, the diodes need to: switch on very fast at low voltage; handle high voltage spikes; and switch off very fast and completely. They also need to be cost-competitive and suited to high-volume production. Read More


Ultra-Thin Body & Box (UTB²) SOI

As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices.

It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report [1] on the importance of the BOX thickness with respect to the electrostatic integrity of SOI devices. The electrostatics of FD SOI devices (we’ll focus on DIBL — Drain Induced Barrier Lowering – a widely used figure of merit for MOSFETs) can be captured within the following simple equation [2]: Read More

ByGianni PRATA

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform

STMicroelectronics recently delivered a 65-nm CMOS SoC design platform for development of next-generation products for low-power, wireless, networking, consumer, and high-speed applications. SOI extensions are at an advanced stage of development and will be available soon, the company said.

ByGianni PRATA

MEDEA+ T206: CMOS SOI for low power logic and RF wireless (CMOSSOI)

Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September.

The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.”

The program, lead by STMicroelectronics, has over 25 partners. For more information, see www.medeaplus.org/web/downloads/profiles/T206_profile.pdf