ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.
Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.
A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) (› 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications Read More
As we approach the end of the roadmap, single gate FD SOI devices with ultra-thin BOX could pre-empt the need for double gate devices.
It is well known that UTB (Ultra Thin Body) devices present improved electrostatic integrity. We were, however, among the first to report  on the importance of the BOX thickness with respect to the electrostatic integrity of SOI devices. The electrostatics of FD SOI devices (we’ll focus on DIBL — Drain Induced Barrier Lowering – a widely used figure of merit for MOSFETs) can be captured within the following simple equation : Read More
STMicroelectronics recently delivered a 65-nm CMOS SoC design platform for development of next-generation products for low-power, wireless, networking, consumer, and high-speed applications. SOI extensions are at an advanced stage of development and will be available soon, the company said.
Ongoing since 2002, the MEDEA+ T206 CMOS SOI project is scheduled to finish up this September.
The objective is: “…to evaluate, design and manufacture a family of CMOS silicon-on- insulator (SOI) circuits for low-power portable, radio frequency (RF) wireless and high-speed applications to compete with more expensive CMOS and bipolar CMOS (BiCMOS) devices.”
The program, lead by STMicroelectronics, has over 25 partners. For more information, see www.medeaplus.org/web/downloads/profiles/T206_profile.pdf •