Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It’s in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance).
If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you’ll want to share this piece with them right away.
Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What’s more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don’t worry that this might be too technical: Sellier’s writing is thoroughly accessible (and engaging!) for anyone in the industry.
He starts with the wafer history, then quickly moves on to the features from the designer’s standpoint. And he puts it all in a business perspective. I can’t recommend this piece enough – even if you think you know everything already yourself, you’re sure to learn something new.
Intento Design is working with STMicroelectronics to bring ID-XploreTM EDA software, which is aimed at solving the critical analog design challenges, to FD-SOI process nodes.
“ID-Xplore is a disruptive EDA software that accelerates analog design and migration processes by at least one order of magnitude. It reduces the cost and latency inherent to analog design. Currently, there is no similar EDA tool on the market covering the analog design challenges like ID-Xplore,” noted Dr. Ramy Iskander, CEO of Intento Design (see the press release here).
ST’s FD-SOI design expertise roots, of course, are as deep as they get. “ST’s decision to work with us confirms the relevance of our solution. We are very excited to work jointly with ST teams to take the most benefit out of FD-SOI technology leveraging ST’s pioneering leadership in this area,” continued Dr. Iskander.
“We’ve already seen the benefits of ID-Xplore in accelerating the design phase of different analog circuits, thanks to the software’s fast and accurate exploration capabilities in advanced FD-SOI processes,” said Thierry Bion, ST’s Hardware Design Director, Aerospace Defense & Legacy Division. “By facilitating IP reuse and sharing of design insights between engineers, ID-Xplore™ is helping our teams significantly accelerate new product introductions.”
ID-Xplore uses the OpenAccess database standard and is fully integrated within the Cadence design environment. The designer’s implicit and explicit knowledge is expressed as technology-independent constraints, bringing the designers back to their core expertise and creativity.
If you want to learn more, the folks over at semiwiki.com have made a number of posts on Intento Design recently. They’re really helpful in understanding what the company does, how and why:
CEO Interview: Ramy Iskander of Intento Design Edit (by Daniel Nenni) – good backgrounder on the company and product.
The Intention View: Disruptive Innovation for Analog Design Edit (by Daniel Nenni) – an excellent interview with Dr. Caitlin Brandon about how the tool works and how it aligns with and supports the way analog designers work.
A New Kind of Analog EDA Company Edit (by Daniel Payne) – Daniel Payne started his career as a circuit designer at Intel, and is now a well-known consultant/expert in the EDA world. Here he explores how ID-Xplore actually works and its “cool new automation features”.
Automakers are currently evaluating prototypes of Viper from AdaSky, a Far Infrared (FIR) thermal camera that embeds custom silicon co-designed with and manufactured by ST in 28nm FD-SOI. The complete sensing solution aims to enable autonomous vehicles to see and understand the roads and their surroundings in any condition.
“With the help of ST, we have created the first high-resolution thermal camera for autonomous vehicles with minimal size, weight, and power consumption–and no moving parts. ST’s access to, and expertise in, ultra-low-power design, IP that is fully qualified for automotive applications, and 28nm FD-SOI technology have been vital to meeting the severe power constraints that would challenge our sensors’ performance,” said Amotz Kats, Vice President Hardware, AdaSky. “We’re in a position to deliver a breakthrough solution to revolutionize and disrupt the autonomous vehicle market because of ST’s mastery of automotive qualification and its strong manufacturing supply chain, which grants reliability, long-term support, and business continuity to car makers throughout the whole life of their production.”
Passive infrared vision, like that in AdaSky’s Viper, when used in a fusion solution, can help close the gaps to provide accurate sight and perception without fail in dynamic lighting conditions, in direct sunlight, in the face of oncoming headlights, and in harsh weather.
The new camera uses an FIR micro-bolometer sensor to detect the temperature of an object. In an ADAS solution, Viper uses proprietary algorithms based on Convolutional Neural Networks to classify obstacles and show them in a cockpit display to give the driver an early warning. This warning comes several seconds earlier than it would when using a conventional sensor in the visible wavelength and is even faster than what is possible with the human eye.
The two companies say that the Far-Infrared thermal camera extends ADAS sensor fusion capability with a new layer of information, helping pave the way to fully-autonomous driving in any condition. Prototypes are now under evaluation by carmakers with initial production targeted for 2020. (Read the full press release here.)
Following the immense success of last year‘s FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up.
ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design.
You’ll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices.
Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond.
The design examples will cover basic building blocks through SoC implementations. A global Q&A session will close the day.
Here’s a little more info on how the day will unfold. Click on the slides to see them in full screen.
FDSOI-specific design techniques for analog, RF and mmW applications – Andreia Cathelin, Fellow, STMicroelectronics
Andreia Cathelin is ST’s key design scientist for all advanced CMOS technologies, and is arguably the world’s leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She’ll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance.
Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications – Frank Zhang, Principal Member of Technical Staff, GlobalFoundries
Frank Zhang has designed chips using GF’s 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements.
Energy-Efficient Design in FDSOI – Bora Nikolic, Professor, UC Berkeley
Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team’s RISC-V chip was cited as one of Dr. Cathelin’s “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He’ll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley’s latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI.
mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies – Sorin Voinigescu, Professor, University of Toronto
Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He’ll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he’ll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he’ll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies.
With over 100 attendees filling every chair in the auditorium, last year’s training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”
2018 will be no different – except that it’s sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks.
Here’s key info you need to sign up. See you there!
When: 27 April 2018, 7:30am – 5pm.
Where: Crowne Plaza San Jose, Milpitas CA (parking is free)
Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)
How to sign up: Click here to go directly to the registration site.
ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.
CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.
As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.
Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.
FD-SOI, said Dr. Cathelin, “…is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in analog, RF/millimeter wave, Analog/Mixed-Signal and digital design. If you’re a designer, you’ll want to check those out.
Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP’s MPW services. Here they are. (You can click on the illustrations to see them in full screen.)
This chip was presented at ESSCIRC ’16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells.
Presented at RFIC ’17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.
Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC ’16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues’ team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn’t need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.
4. Matched Ultrasound Receiver in 28FDSOI
Presented at ISSCC ’17 (with an extended relative paper at JSSC ’17) by M-C Chen et al with Professor Boris Murmann’s team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It’s a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “…an emerging medical imaging modality based on optical excitation and acoustic detection.” It’s used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.
5. SleepTalker – 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC
Presented at VLSI ’16 and JSSC ’17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that’s a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “…threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. […] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”
This massive MIMO chip was presented at ISSCC ’17 by a team from Professors Liang Liu and Ove Edforss at the Lund University in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can’t be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team’s intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”
7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
Today’s solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10’s to several 1OO’s of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC ’17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “…the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”
As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC ’16 and JSSC ’17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “… extremely fine-grained (<1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.) These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium’s FD-SOI Training Day in Silicon Valley, 27 April 2018 – click here for sign-up information.)
At the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST’s SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS & micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).
CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don’t hesitate to inquire, as they’ll be adding more.
For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report.
For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here. Training kits and tutorials will be available in Q3 of this year.
And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.
So lots of terrific SOI resources for CMP – check it out!
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Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.
FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read:
But, if you don’t have time to read them all right away, here are some highlights to tide you over til you do.
Ed Sperling at SemiEngineering sees FD-SOI adoption “… gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.”
After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won’t necessarily be the billions of units per chip needed to amortize exorbitant design costs.
In particular, for FD-SOI adoption he cites, “…the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF’s Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.)
ST’s Giorgio Cesana makes an interesting point about body biasing (that I hadn’t hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that’s not a problem after all.)
Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They’re looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that….
In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “…as new markets open up, chipmakers are finding themselves much closer to the application than in the past.”
All in all a great read – don’t miss it.
David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF’s Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF’s 22FDX (FD-SOI) technology at Mobile World Congress.
For example, Nanotel Technology is using 22FDX to “…reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company’s CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI.
Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There’s no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company’s CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM.
Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “…the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.”
Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia & Europe). The IP covers integrated baseband, power management, RF radio and front-end components.
Lammers also cited Anubhav Gupta, GF’s director of strategic marketing and business development for IoT, AI & Machine Learning. He said they’ve got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated.
In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech’s Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you’re looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.”
Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They’ll be in risk production in early 2019.
Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”.
All in all – products and press – it’s a really fine Q1.
EDA companies Cadence, Synopsys and Silvaco all gave excellent presentations at the SOI Consortium forums in Nanjing and Shanghai.
Here’s a recap of what the Cadence folks said. (I’ll cover the Synopsys and Silvaco presentations in my next posts.)
At the Shanghai FD-SOI Forum. Dr. Qui Wang, VP & Chief of Staff, talked about FD-SOI Foundry Enablement: From Concept to Mass Production. Cadence, he reminded the packed ballroom, is not just EDA, but also system design enablement targeting verticals. “We’re ready!” he stated.
In the last three years, they’ve done a lot of work on FD-SOI, he said, even working with ARM, GF and Dream Chip on the demo board as a reference design for automotive or vision applications, to show real data to their customers. It uses a quad implementation of the configurable Tensilica Vision P6 core.
To simplify back biasing for the library folks, they worked with the foundries to create interpolations. And as Cadence is traditionally strong in RF/mixed-signal, there’s a new back-biasing tool to simplify board-chip communications, and make the bridge between power and thermal analysis.
Jonathon Smith, Director of Strategic Alliances at Cadence, presented Enabling an Interconnected Digital World — Cadence EDA & IP Update at the Nanjing SOI summit. As he explained, his job is to ensure that design customers can use Cadence tools effectively, not just with Cadence IP, but also with 3rd party IP for the foundry nodes.
He pointed out that the numbers for IoT predictions vary widely, and that industrial IoT (IIoT) will probably account for about 10% of the market. What is sure is that it will contain a large mixed-signal component (RF/digital/analog) and complex packaging.
His customers want to know how fast and easy it is to work in FD-SOI. “Cadence custom and digital tools are ready for FD-SOI,” he said. They have the PDKs and tech files, and the EDA tools are enabled. The reference flows (both digital and custom analog) are tested and ready (Cadence customers who use p-cells and RF look especially for a good mixed-signal flow).
Customers also ask for proof points, and want to know the number of tape-outs they’ve done, performance benchmarks for working silicon and proven IP: this is what gives designers confidence, he said. Examples like Dream Chip’s Computer Vision Processor Chip Design for automotive ADAS CNN applications in 22nm FD-SOI (which they announced at Mobile World Congress in 2017 – see the press release here) have really helped build confidence further, he observed. (In case you missed it, DreamChip presented at the Silicon Valley SOI event in April 2017 – you can get that presentation here.)
Cadence sees SOI as a driving force in IoT markets. They’ve also had some big digital wins recently, he added, and have made some major announcements with the foundries.
For example, in September, they announced that their set of Design for Manufacturing (DFM) tools (signoff solutions) are now qualified on Samsung’s 28nm FD-SOI. This enables customers to create complex, advanced-node designs for the automotive, mobile, IoT, high-performance compute (HPC) and consumer markets (read the press release here). The Samsung Foundry’s PDKs for 28nm FD-SOI are available for download now and incorporate the Cadence Litho Physical Analyzer (LPA), Physical Verification System (PVS) and Cadence CMP Predictor (CCP). In addition to signoff quality, the Cadence DFM tools offer an integration with the Virtuoso® platform and the Innovus™ Implementation System, providing designers with automated fixing capabilities and overall ease of use.
And in October, Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for GlobalFoundries 22FDX™ (read the press release here). The Cadence® tools enable advanced-node customers across a variety of vertical markets—including automotive, mobile, IoT and consumer applications—to use GF’s FD-SOI architecture to optimize power, performance and area (PPA).
Cadence tools for ST’s 28nm FD-SOI foundry process were ready in 2016, btw – there’s a nice video testimonial from ST on power signoff, for example, which you can see here.
A recent article in Semiconductor Engineering announced The Return of Biasing (read the whole thing here). It’s back because of the quest to build more powerful mobile devices that support long battery life. And with FD-SOI designers can once again easily use what is essentially an old design trick for controlling threshhold voltage (Vt). (In the simplest terms, Vt is the point at which a transistor turns on or off.)
This piece is a really good read if you want to know why body biasing is back in the game, and when and how it’s used. It gets fairly technical, but it’s also very clear. SemiEngineering’s Ann Steffora Mutschler really explores the advantages and issues in interviews with experts at ARM and ST, among others. They explained, for example, the differences between leveraging body biasing on bulk and FD-SOI.
By way of background, btw, for much of the history of chip design, body biasing was standard operating procedure. But, as ST Marketing Director Giorgio Cesana noted, body biasing effectively ended at the 40nm node for bulk, and is unworkable in FinFETs. But with FD-SOI, you can not only lower the Vt, but greatly expand the Vdd (supply voltage) range.
ARM Fellow Rob Aitken notes that, “If you are using an FD-SOI type of process, then biasing the substrate is fairly straightforward because the insulator is just sitting there. There are some mechanics to doing it, but the process is tuned to do it easily.”
You really will want to read the whole piece to get a fuller understanding of why and how the use of body biasing is once again on the rise.
The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.
These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.
Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:
Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.
“The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.
The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.
FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.
Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.