ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.
CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.
As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.
Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.
FD-SOI, said Dr. Cathelin, “…is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in analog, RF/millimeter wave, Analog/Mixed-Signal and digital design. If you’re a designer, you’ll want to check those out.
Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP’s MPW services. Here they are. (You can click on the illustrations to see them in full screen.)
This chip was presented at ESSCIRC ’16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells.
Presented at RFIC ’17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.
Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC ’16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues’ team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn’t need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.
4. Matched Ultrasound Receiver in 28FDSOI
Presented at ISSCC ’17 (with an extended relative paper at JSSC ’17) by M-C Chen et al with Professor Boris Murmann’s team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It’s a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “…an emerging medical imaging modality based on optical excitation and acoustic detection.” It’s used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.
5. SleepTalker – 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC
Presented at VLSI ’16 and JSSC ’17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that’s a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “…threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. […] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”
This massive MIMO chip was presented at ISSCC ’17 by a team from Professors Liang Liu and Ove Edforss at the Lund University in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can’t be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team’s intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”
7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
Today’s solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10’s to several 1OO’s of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC ’17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “…the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”
As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC ’16 and JSSC ’17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “… extremely fine-grained (<1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.) These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium’s FD-SOI Training Day in Silicon Valley, 27 April 2018 – click here for sign-up information.)
At the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST’s SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS & micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).
CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don’t hesitate to inquire, as they’ll be adding more.
For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report.
For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here. Training kits and tutorials will be available in Q3 of this year.
And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.
So lots of terrific SOI resources for CMP – check it out!
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Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.
Over a hundred chip designers packed the room for the SOI Consortium’s recent FD-SOI Design Techniques Tutorial Day. Five professors and scientists from top institutions covered design techniques with real examples in digital, mixed-signal, analog, RF, mmW and ULV memory.
Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q&A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.”
Many of the questions pertained to body biasing, which prompted STMicroelectronics Fellow and Professor Andreia Cathelin to state what may well have been the take-away of the day. “Body biasing is not an obligation,” she said. “It’s an opportunity.”
The tutorial, sponsored by both Samsung and GlobalFoundries, was hosted by Samsung at their San Jose headquarters. But as this was a paying event, the presentations are only available to those who attended. Having had the good fortune to attend, I can give you a quick recap of some of the highlights.
Professor Cathelin set the stage with a basic overview of FD-SOI design for analog, mixed-signal and mmW.
FD-SOI is a perfect match for the many up and coming SOCs that are often half analog and/or RF and mmW. She explained how FD-SOI makes the analog designer’s life much easier (no small feat, since analog can seem rather like blackbox magic to those on the digital side). FD-SOI improves: performance (even at high frequencies), noise, short device efficiency and brings in a new very efficient transistor knob through the Vt (threshold voltage) tuning range. She also explained and gave numerous real examples implemented in ST’s 28FDSOI on how:
For mmW design, the transistor should operate at Lmin, and hence you get excellence performance in terms of both transition frequency (Ft – set by the technology node) and maximum frequency (Fmax – what the designer can really get in the gain vs. speed trade-off). This can be conjugated with the fact that the back-end of line, despite the very fine nm node, takes advantage of the SOI features and brings in very decent quality factors.
For mixed-signal/high-speed design, she showed how and why FD-SOI gives you improved variability, a fantastic switch performance, and reduced parasitic capacitance. All these permit state of the art results in high-speed data converters, or, for example, lower frequency implementations which do not need any specific calibration for best in class linearity and ENOB (effective number of bits).
She also presented details on the CEA-Leti electrical models which are now the reference stand point (Leti-UTSOI2) for any FDSOI technology, and are implemented in several industrial Design Kits such those from ST.
Next on tap was a very lively talk with almost 60 slides by Professor Sorin Voinigescu of U. Toronto. He focused on how to use the main features of FD-SOI for efficient design of RF, mm-wave and broadband fiber-optic SOCs. We’re talking high-speed/high-frequency here, and he had real examples of chips fabbed in ST’s 28FDSOI and some simulated in GlobalFoundries’ 22FDX technology.
He examined layout issues and gave measurement tips and tricks, noting that there are a lot of things you can do in FD-SOI that you can’t do in bulk. It’s also easier to get high linearity in FD-SOI – yet another reason that he really likes it. Plus he sees it as competitive in terms of scaling even past 7nm.
Professor Joachim Rodrigues of Lund University in Sweden (the largest university in Scandinavia) talked about Design Strategies for ULV memories in 28nm FD-SOI (ST’s FD-SOI technology). Noting that SRAMs eat a lot of area in an SOC, he first proposed a standard cell-based memory (SCM) in 28nm FD-SOI that cut memory area by 35% and reduced leakage by 70%.
He then talked about other chips he and his team have presented at the world’s top chip conferences, including an ultra-low voltage (ULV) SRAM. For that chip they lay claim to having the best write performance in ULV in sub-65nm (15MHz at 240mV), and the best performing read capability across all technologies (30MHz at 240mV). In each case, he explained the fundamental design considerations, concepts and trade-offs.
Professor Borivoje “Bora” Nikolic of UC Berkeley is an expert in body-biasing for digital logic. He and his team have designed ten chips in ST’s 28nm FD-SOI, and they’re now working on their 8th generation of energy-efficient SOCs. During his 90-slide (!) tutorial, Energy-Efficient Processors in 28nm FDSOI, he covered: digital logic (including implementation and adaptive tuning of cores for optimal energy efficiency); SRAM and caches (design scenarios and results compared to bulk); supply (generating, switching and analog assists); back bias (how it’s generated and how to use it). He finished with (60 slides of!) design examples and the results they got for power (including adaptive voltage scaling) and performance. He said to be on the lookout for upcoming publications on (even more!) chips, as well as new work on 22nm designs.
Even if you don’t know anything about mixed-signal design, you can walk away from an hour-long lecture by Professor Boris Murmann of Stanford with a good understanding of what it’s all about. In his talk, Pushing the Envelope in Mixed-Signal Design Using FD-SOI, he explained how a mixed-signal person thinks about FD-SOI, and how the different metrics and sweetspots vary depending on what you’re working on. From there it was the deep dive, as he got into the heart of his talk: simulated transition frequency vs. gm/lD. He explained that while some things might seem counter intuitive (like long channels are more efficient for very low Ft requirements), it’s all related to electrostatics. It’s not yet well explained in the literature, he said, but it should be a big deal. And he explained why with FD-SOI, you don’t have to design for the worst case. He then talked about where he sees things going – he sees a very bright future indeed for FD-SOI and analog as computing moves into very low-power neural networks. In the end, he said, it all boils down to the FD-SOI performance benefits with respect to better gate control. This translates into “significant improvements” for many mixed-signal/RF building blocks.
All in all, it was a really terrific day. BTW, this tutorial day followed a full-day FD-SOI Symposium in Silicon Valley. Click here to read about that.
Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.
On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.
The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)
The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.
(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)
Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.
If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.
She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology. Then the focus shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing. For each category of circuits (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.
Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics. The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.
Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.
Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.
For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.
Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.
Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.
If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.
The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.
So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:
As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).
If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.
As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.
In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:
For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).
In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.
As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.
In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.
So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
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*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.
In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.
Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).
The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.
The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.
Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.
This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.
IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.
Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)
New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.
In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.
FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.
FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.
Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.
In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.
“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.
He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.
Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).
And clearly, he’s a man who knows the future.
Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.
Is there a place for FinFETs? Of course there is. If it’s a really big digital chip – no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.
But is that really where most designs are?
If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.
Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.
Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.
The session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.
And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”
In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:
The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
There you have it!
Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).
Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.
So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
SOI-3D-Subthreshold Microelectronics Technology Unified Conference
6-9 October 2014
Westin San Francisco Airport, Millbrae, CA
Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.
The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.
The 2014 edition of the conference already promises a rich content of high-level presentations.
The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.
Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.
On the same webpage, more information is given about the various dedicated sessions.
There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.
The Committee will review papers submitted by May 26 in the three following focus areas of the conference:
Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.
The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.
Paper submission deadline: 26 May 2014
Notification of acceptance: 23 June 2014
Short course date: 6 October 2014
Conference date: 6 – 9 October 2014
More details are available on the S3S website.