Tag Archive strain

ByGianni PRATA

Leti Develops 22nm FD-SOI Local-strain Techniques to boost performance and lower power consumption

CEA-Leti announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed or lower power consumption and improved performance. (For more details, read the press release here.) Targeting the 22/20nm node, the local-strain solutions are dual-strained technologies: compressive SiGe for PFETs and tensile Si for NFETs. In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing.

The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel. Strained channels enable an increase in the on-state current of CMOS transistors. As a result, chips can deliver more speed at the same power, or reduce consumed power for longer battery life at the same performance. The first technique relies on strain transfer from a relaxed SiGe layer on top of SOI film. The second technique is closer to strain memorization methods and relies on the ability of the BOX to creep under high-temperature annealing.

“These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory.


The SOI Papers at VLSI ’14 (Part 2):

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!


(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.


4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.


6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.


8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalon et al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.


9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.


13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.


13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.


17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.


18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.


18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.


18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.


SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.



(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)



C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.


The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four papers in the Highlights Sessions covered SOI devices for the 10 and 14nm nodes.

There were so many great SOI-based papers that we’re going to cover this conference in two posts.  This post covers the three big 14nm FD-SOI and 10nm FinFET papers. Summaries and abstracts of all the others will be covered in Part 2 (click here to read Part 2).  Please note that as of this posting date, the papers are not yet available from the IEEE Xplore site – but they should be shortly.

Read on!

Top SOI Highlights from the Symposium on VLSI Technology

2.3: 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications. O. Weber et al. (STMicroelectronics, CEA-LETI, IBM)

This is the big paper we’ve been waiting for – the one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs. We still don’t have a side-by-side FD-SOI v. bulk FinFET comparison, as there is scant data at comparable leakage on bulk FinFETs at 14nm publicly available with which to compare. But based on what they’ve been seeing and some extrapolation, the FD-SOI  technology developers see the figures presented in this paper as a big win.  We’ve already seen hints of this in a recent ASN piece (click here to see that one) showing 14nm FD-SOI matching 14nm bulk for performance and coming in at a much lower cost.  Now in terms of performance, here’s the VLSI paper detailing the FD-SOI side of the story.

The authors confirm a scaling path for FD-SOI technology down to 14nm, using strain-engineered FD-SOI transistors. Compared to 28-nm FDSOI, this work provides an 0.55x area reduction from scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back-bias, an additional 40% dynamic power reduction for ring oscillators is experimentally demonstrated. Moreover, a full single-port SRAM is described, including a 0.081 μm2 high-density bitcell and two 0.090 μm2 bitcell designs used to address high-performance and low-leakage/low Vmin requirements.


(Courtesy: VLSI Symposia)


TEM of an FD-SOI nMOS transistor, showing gate-to-drain capacitance components and experimental values. From 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications (O. Weber et al., STMicroelectronics, CEA-LETI & IBM)






2.2: A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI.  K.-I. Seo et al.  (Samsung, IBM, ST, GF, UMC)

This paper covers the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing. Targeting low-power and high-performance, it offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 μm2 SRAM bit-cell – and this part was on SOI –  was reported with a low corresponding static noise margin of 140 mV at 0.75 V.  The team developed intensive multi-patterning technology and various self-aligned processes with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce.


(Courtesy: VLSI Symposia)


Projected scaling trend, featuring the tightest contacted poly pitch (CPP=64 nm) and metallization pitch (Mx=48 nm) ever reported, on both bulk and SOI substrates. From A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, by K.-I. Seo et al.  (Samsung, IBM, ST GF, UMC)





2.4: Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

The authors demonstrated high performance (HP) s-SiGe pMOS pMOSsfinFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. They also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and L G~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe FinFETs are strong candidates for future HP and low-power applications.


(Courtesy: VLSI Symposia)


TEM images of the most aggressively scaled SiGe FinFET reported to date with a fin width of ~8nm and gate length of ~15nm. From Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)




Rump Sessions

There were also two rump sessions held during the conference, which were co-chaired by Soitec CTO Carlos Mazure. The SOI ecosystem was well-represented, the rooms were packed and the debate lively.

Rump Session 1: Who gives up on scaling first: device and process technology engineers, circuit designers, or company executives?  Which scaling ends first – memory, or logic? Panelists: M. Bohr, Intel; M. Cao, TSMC; J. Chen, Nvidia; S-H Lee, Hynix; T-J King Liu, UC Berkeley; K. Nii, Renesas: R. Shrivastava, Sandisk; H. Jaouen, STMicroelectronics; E. Terzioglu, Qualcomm

The take-away here is that the majority of panelists and attendees see company executives giving up on scaling in the face of rising costs.

Rump Session 2: 450 mm, EUV, III-V, 3D; All in 7nm? Are you serious?!  Panelists:  W. Arnold, ASML;
 R. Gottscho, Lam Research; K. Hasserjian, AMAT; S. Iyer, IBM;
 C. Maleville, Soitec; A. Steegen, IMEC

The general consensus was that 3D integration is needed and will be adopted at the 7nm node due to delays and the high cost of the EUV and III-V, and the lack of 450mm wafer supply and support.


IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices.

Brief summaries, culled from the program (and some of the actual papers) follow.



9.4 2nd Generation Dual-Channel Optimization with cSiGe for 22nm HP Technology and Beyond (IBM)

This paper about performance boosters is applicable to all flavors of SOI-based devices, including FinFET, planar FD-SOI and partially-depleted SOI. At 22nm for high-performance (HP), IBM is still doing the traditional partially-depleted (PD) SOI. At 14nm, when they go to SOI-FinFETs, one of the channel stressors to boost performance is Silicon-Germanium (cSiGe). To better understand the physics, layout effects and impact of cSiGe on device performance, IBM leveraged their 22nm HP technology to do a comprehensive study. They got a 20% performance boost and 10% Short Channel Effect (SCE) improvement, and showed that this 2nd generation high-performance dual-channel process can be integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.


13.5 Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs  (GlobalFoundries, IBM)

SOI FINFETs are very attractive because of their added immunity to Vt variability due to undoped channels. However, circuit level performance also depends on the effective current (Ieff) variability. According to the advance program, “A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.”


20.5 Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs (AIST, Nissin Ion Equipment)

In this paper, the researchers thoroughly investigated the impact of the heated ion implantation (I/I) technology on HK/MG SOI FinFET performance and reliability, which it turns out is excellent. They demonstrated that “…the heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that the heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability, and bias temperature instability (BTI) for both nMOS and pMOS FinFETs in comparison with conventional room temperature I/I.”


26.2:  Advantage of (001)/<100> oriented Channel to Biaxial and Uniaxial Strained Ge-on-Insulator pMOSFETs with NiGe S/D (AIST)

In this paper about boosters in fully-depleted planar SOI and GeOI based devices, the researchers “compared current drivability between (001)/<100> and (001)/<110> strained Ge-on-insulator pMOSFETs under biaxial and uniaxial stress.” They experimentally demonstrated for the first time that in short channel (Lg < 100 nm) devices, <100> channels exhibit higher drive current than <110> channels under both the biaxial- and the uniaxial stress, in spite of the disadvantage in mobility, although this is not the case with longer channel devices. The advantage is attributable to higher drift velocity in high electric field along the direction and becomes more significant for shorter Lg devices. The strained-Ge (001)/<100> channel MOSFET have a potential to serve as pFET of ultimately scaled future CMOS.


33.1 Simulation Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability (Invited) (U. Glasgow, GSS, IBM)

With ever-reducing design cycles and time-to-market, design teams need early delivery of a reliable PDK before mature silicon data becomes available. This paper shows that the GSS ‘atomistic’ simulator GARAND used in this study provides accurate prediction of transistor characteristics, performance and variability at the early stages of new technology development and can serve as a reliable source for PDK development of emerging technologies, such as SOI FinFET.  Specifically, the authors report on, “…a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modeling strategy is developed for early delivery of a reliable PDK, which enables TCAD- based transistor-SRAM co-design and path finding for emerging technology nodes.” 



1.3: Smart Mobile SoC Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities (Qualcomm)

In this plenary presentation, Geoffry Yeap, VP of Technology at Qualcomm gave a perspective on state of the art mobile SoCs and RF/analog technologies for RF SOCs. The challenge, he said in his paper, is “…lower power for days of active use”. He cited the backgate for asymmetric gate operation and dynamic Vt control, noting that FinFETs lack an easy way to access the back gates. “This is especially crucial when Vdd continues to scale lower to a point that there is just not sufficient (Vg-Vt) to yield meaningful drive current,” he continued. While he sees FD-SOI “very attractive”, he is concerned about the ecosystem, capacity and starting wafer price.

With respect to RF-SOI, the summary of his talk in the program stated, “Cost/power reduction and unique product capability are enabled by RF front end integration of power amplifiers, antenna switches/tuners and power envelope tracker through a cost-effective RF-SOI instead of the traditional GaAs.”


Advanced Devices

Post-FinFETs, one of the next-generation device architectures being heavily investigated now is  gate-all-around (GAA). While FinFETs have gate material on three sides, in GAA devices the gate completely surrounds the channel. A popular fabrication technique is to build them around a nanowire, often on an SOI substrate.

4.4 Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling  (Forschungszentrum Jülich, U. Udine, Soitec)

This is a paper about a strained Si (sSi) nanowire array Tunnel FETs (TFETs). The researchers demonstrated that scaled gate all around (GAA) strained Si (sSi) nanowire array (NW) Tunnel FETs (TFETs) allow steep slope switching with remarkable high ION due to optimized tunneling junctions. Very steep tunneling junctions have been achieved by implantations into silicide (IIS) and dopant segregation (DS) with epitaxial Ni(AlxSi1-x)2 source and drain. The low temperature and pulse measurements demonstrate steep slope TFETs with very high I60 as TAT is suppressed. GAA NW TFETs seem less vulnerable to trap assisted tunneling (TAT). Time response analysis of complementary-TFET inverters demonstrated experimentally for the first time that device scaling and improved electrostatics yields to faster time response.



(image courtesy: IBM, IEEE/IEDM)

20.2 Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond (IBM)

Record Silicon Nanowire MOSFETs: IBM researchers described a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10-nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured an incredible 30-nm SiNW pitch (the spacing between adjacent nanowires) with a gate pitch of 60 nm. Devices with a 90-nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.



26.4 FDSOI Nanowires: An Opportunity for Hybrid Circuit with Field Effect and Single Electron Transistors (Invited) (Leti)

This paper is about nanowires and single electron transistors (SET).  As indicated in the  program, “When FDSOI nanowires width is scaled down to 5nm, the nanowires can encounter a dramatic transition to single electron transistor characteristics. This enables the first room temperature demonstration of hybrid SET-FET circuits thus paving the way for new logic paradigms based on SETs. Further scaling would rely on deterministic dopant positioning. We have also shown that Si based electron pumps using tunable barriers based on FETs are promising candidates to realize the quantum definition of the Ampere.”


26.6 Asymmetrically Strained High Performance Germanium Gate-All-Around Nanowire p-FETs Featuring 3.5 nm Wire Width and Contractable Phase Change Liner Stressor (Ge2Sb2Te5) (National U. Singapore, Soitec)

In this paper about GAA and nanowires, the researchers report “…the first demonstration of germanium (Ge) GAA nanowire (NW) p-FETs integrated with a contractable liner stressor. High performance GAA NW p-FET featuring the smallest wire width WNW of ~3.5 nm was fabricated. Peak intrinsic Gm of 581 μS/μm and SS of 125 mV/dec was demonstrated. When the Ge NW p-FETs were integrated with the phase change material Ge2Sb2Te5 (GST) as a liner stressor, the high asymmetric strain was induced in the channel to boost the hole mobility, leading to ~95% intrinsic Gm,lin and ~34% Gm,sat enhancement. Strain and mobility simulations show good scalability of GST liner stressor and great potential for hole mobility enhancement.”


III-V, More Than Moore and Other Interesting Topics

28.5 More than Moore: III-V Devices and Si CMOS Get It Together (Invited) (Raytheon)

This is continuation of a major ongoing III-V and CMOS  integration project that Raytheon et al wrote about in ASN five years ago (see article here).  As noted in the IEDM program, the authors “…summarize results on the successful integration of III-V electronic devices with Si CMOS on a common silicon substrate using a fabrication process similar to SiGe BiCMOS. The heterogeneous integration of III-V devices with Si CMOS enables a new class of high performance, ‘digitally assisted’, mixed signal and RF ICs.


31.1 Technology Downscaling Worsening Radiation Effects in Bulk: SOI to the Rescue (Invited) (ST)

In this paper, the authors explore the reliability issues faced by the next generation of devices.  As they note in the description of the paper in the program, “Extrinsic atmospheric radiations are today as important to IC reliability as intrinsic failure modes. More and more industry segments are impacted. Sub-40nm downscaling has a profound impact on the Soft Error Rate (SER) of BULK technologies. The enhanced resilience of latest SOI technologies will fortunately help leveraging existing robust design solutions.”


13.3 A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications (ST, Luxtera)

Luxtera’s work on Silicon Photonics and now products based on integrated optical communications has been covered here at ASN for years. In this paper Luxtera and ST (which now is Luxtera’s manufacturing partner) present a low-cost 300mm Silicon Photonics platform for 25Gb/s application compatible with 3D integration and featuring competitive optical passive and active performance. This platform aims at industrialization and offering to system designers a wide choice of electronic IC, targeting markets applications in the field of Active optical cables, optical Modules, Backplanes and Silicon  Photonics Interposer.


Irisawa (2.2) Fig.9

The graph above shows the high electron mobility of Triangular MOSFETs with InGaAs Channels. (Image courtesy: AIST, IEEE/IEDM) 


2.2. High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures (AIST, Sumitomo, Tokyo Institute of Technology)

InGaAs is a promising channel material for high-performance, ultra-low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration. A research team led by Japan’s AIST built triangular InGaAs-on-insulator nMOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30 nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 μA/μm at a 300-nm gate length, showing they have great potential for ultra-low power and high performance CMOS applications.


16.4. High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator Tri-gate MOSFETs with high short channel effect immunity and Vth tenability (Sumitomo, Tokyo Institute of Technology)

This III-V paper investigates the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. “It was found that Tbody scaling provides better SCEs control, whereas Tbody scaling causes μfluctuation reduction. To achieve better SCEs control, Tchannel scaling is more favorable than Tbuffer scaling, indicating QW channel structure with MOS interface buffer is essential in InAs-OI MOSFETs. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/μm. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control. These results strongly suggest that the Tri-gate ETB III-V-OI structure is very promising scaled devices on the Si platform to simultaneously satisfy high performance high SCE immunity and Vth tunability.”

11.1 A Flexible Ultra-Thin-Body SOI Single-Photon Avalanche Diode (TU Delft)

This is a paper on flexible electronics for display and imaging systems. “The world’s first flexible ultra-thin-body SOI single-photon avalanche diode (SPAD) is reported by device layer transfer to plastic with peak PDP at 11%, DCR around 20kHz and negligible after pulsing and cross-talk. It compares favorably with CMOS SPADs while it can operate both in FSI and BSI with 10mm bend diameter,” say the researchers.


11.7 Local Transfer of Single-Crystalline Silicon (100) Layer by Meniscus Force and Its Application to High-Performance MOSFET Fabrication on Glass Substrate (Hiroshima U.)

In this is a paper on flexible electronics for display and imaging systems, the researchers “…propose a novel low-temperature local layer transfer technique using meniscus force. Local transfer of the thermally-oxidized SOI layer to glass was carried out without any problem. The n-channel MOSFET fabricated on glass using the SOI layer showed very high mobility of 742 cm2V-1s-1, low threshold voltage of 1.5 V.  These results suggest that the proposed (meniscus force-mediated layer transfer) technique (MLT) and MOSFET fabrication process opens up a new field of silicon applications that is independent of scaling.”


Note: the papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.


Special thanks to Mariam Sadaka and Bich-Yen Nguyen of Soitec for their help and guidance in compiling this post.


The FD-SOI Papers at IEDM ’13

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.

Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.

9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries) 

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012


Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 


and below.

The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”


7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.


20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.


12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.


33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.


2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.


5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (Tw) than predicted by the T6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)


The IEEE S3S Conference Delivered Impressive Technical Content

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EDS Logo PMS3015_revu


A view of the Bay from Cannery row, Monterey, CA.

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.

The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).

Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.


Chart from A. Paul (GF) showing benefits of Fin width scaling

The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)



The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.

sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).

An impressive hot topics session was dedicated to RF CMOS.

J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.

Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.

The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).

The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.

The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.


Snapshot from Dr M. Farooq’s (IBM) presentation (3DI shortcourse)

3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.


The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.

Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.


SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).


GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET

According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die cost by 10%. (Both HPP and FD-SOI are HKMG/GateFirst).


Moving to 20nm, the graph indicates that FD-SOI gets an additional 25% performance increase: that’s terrific. This slide doesn’t give a performance increase figure for 20LPM, but it’s clearly way below 20nm FD-SOI.

Now there are no actual figures given for die cost at 20nm, but the position on the graph indicates that the shrink to 20nm on FD-SOI costs substantially less than the cost for shrinking on bulk.   Later in the presentation, he indicated that a big part of the savings is in masks – FD-SOI requiring 10 fewer masks than bulk.

Interesting to note the position of 14XM, which is a bulk FinFET. Again, no actual figures are given, but die cost is substantially higher. However the relative performance increase does not appear to be very significant.

The presentation was made during the FD-SOI Workshop following VLSI in Kyoto, Japan. It is available from the SOI Consortium website.

Other presentations

Looking ahead to 14nm FD-SOI for high performance, ST’s  Laurent Le Pailleur showed this interesting slide in his Kyoto Workshop presentation, 28nm FD-SOI Industrial Solution: Overview of Silicon Proven Key Benefits – again, lots of masks saved:


There are other presentations from the Workshop available on the Consortium website, including a terrific short course by David Jacquet of ST entitled Architectural choices & design-implementation methodologies for exploiting extended FD-SOI DVFS & body-bias capabilities.

For those wanting to know more about FinFETs on SOI, Terry Hook of IBM expanded on his excellent ASN article in a presentation entitled Elements for the Next Generation FinFET CMOS Technology. In particular, there are lots of clear explanations about why SOI makes a difference, and the role of wafer-level strain (aka “strained silicon directly on insulator” – which IBM calls SSDOI)  wafers by Soitec.



Which will hit the 14nm jackpot first: FD-SOI or FinFET? Gauntlet down. Race on.

STMicroelectronics CTO Jean-Marc Chery threw down the gauntlet when he told Electronics Weekly, “We must be ready with 14nm FD-SOI before anyone has FinFET at 14nm.”

Can they do it?

Yes, they can.

Unlike FinFETs, Planar FD-SOI is not a disruptive technology – FD-SOI is an extension of the planar CMOS we all know and love.  Although the concept is over a decade old, the current technical development is moving at lightspeed.

When ST ported 28nm bulk to 28nm FD-SOI, they did it soup-to-nuts – including wafer processing – in under six months, with amazing results. At VLSI Kyoto, they reported that starting from a direct porting of a bulk planar CMOS SRAM design, the improvement in read current Iread was up to +50% (@Vdd=1.0V) and +200% (@ Vdd=0.6 V), respectively, compared with the original 28nm Low-Power (LP) CMOS technology.

processed 300mm 28nm FD-SOI wafer

A processed 300mm 28nm FD-SOI wafer on display at ST’s Technoday (Paris, June 2013)

The laying of the foundation – writing compact and SPICE models – has long been done. As Leti’s Olivier Rozeau explained in his article about Leti’s 28nm FD-SOI Compact models a few years ago in ASN, robust models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing.

SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to committing a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).

And when Mentor moved the Leti models to robust circuit simulators, they did it in under two years. Phenomenal! Leti’s 14nm models are now done, and the PDKs will be ready in Q3’13.

In fact, Leti is now working on models for 10nm FD-SOI, for which they’ll have PDKs in a year. That means all systems are go for 10nm FD-SOI in 2016.  (And by the way, Leti CEO Laurent Malier also says that for boosting pFETs with SiGe, they’re seeing better results with FD-SOI than bulk FinFETs.)

What about manufacturing? Fabs typically take about a year to re-characterize their processes for a shrink.  Moving from planar 28nm to 14nm FD-SOI is a straight shrink of what is essentially a legacy technology. Again, no showstoppers.

From a manufacturing standpoint, there are no gotchas, no special equipment. As Chery noted in an ASN interview last fall, “On the manufacturing side, FD-SOI does not introduce additional complexity: on the contrary, process steps are reduced and thus cycle time.”

The ultra-thin wafers have been ready for years, and have multiple sources including Soitec and SEH.

In terms of design, the design flows, methodologies and tools are the same as designers have always used. And, with FD-SOI, biasing efficiency (not possible in FinFETs) is an added bonus. ST has published figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at low power 0.6V – especially good news for anything with a battery.

In fact, Leti’s Malier recently highlighted that the advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!

Leti’s finding that boosters like strain add another 10% to the performance figures: so overall with boosters they’re seeing +40% performance at the same supply voltage (Vdd) moving to 14nm, and another 30% moving to 10nm.

In discussing the two flavors of FD-SOI they have planned, Subi Kengeri, Vice President of Advanced Technology Architecture at GlobalFoundries points to this ST slide regarding timing:


The icing on the cake is the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In particular, the recently announced €360 million FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe) is a plum. While the European workforce will certainly be the first to benefit from this, it is a strong endorsement of FD-SOI and really good news for the entire FD-SOI ecosystem.

Chery sees big opportunities for FD-SOI. At the ST Technodays (4 June 2013), he told ASN he’s targeting mobile, as well as networking/servers, gaming and apps, including set-top boxes. (And he also hinted that we should be on the look-out for some big announcements.)

So those folks that give bulk FinFETs an edge in the race to 14nm better keep the pedal to the metal and their eyes on the road as FD-SOI has a tuned engine and a smooth track. Buckle your seatbelts: the race is on.

ByAdele Hars

Fully-Depleted SOI (and more) at VLSI (Kyoto): some knock-your-socks-off papers

Look for some breakthrough FD-SOI and other excellent SOI-based papers coming out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14).

By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both are presented in “Jumbo Joint Focus” sessions.

Here’s a quick preview.

Papers in the Jumbo-Joint Focus Sessions

JJ2-3: FDSOI Process/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs, R. Ranica et al., STMicroelectronics & CEA-LETI

In this paper from STMicroelectronics and CEA-LETI, six Transistor SRAM (6T- SRAM) cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage (0.197µm2) purposes are fabricated with 28 nm node FDSOI technology for the first time. Starting from a direct porting of bulk planar CMOS design, the improvement in read current Iread has been confirmed up to +50% (@Vdd=1.0V) & +200% (@ Vdd=0.6 V), respectively, compared with 28 nm Low-Power (LP) CMOS technology. Additionally, -100mV minimum operating voltage (Vmin) reduction has been demonstrated with 28 nm FDSOI technology. Alternative flip-well and single well architecture provides further speed and Vmin improvement, down to 0.42V on 1Mb 0.197µm2 . Ultimate stand-by leakage below 1pA on 0.120 µm2 bitcell at Vdd=0.6V is finally reached by taking the full benefits of the back bias capability of FDSOI.

Cross-sectional and plain view of FDSOI SRAM cells for High Density (0.120 µm2), High Current (0.152 µm2) and Low Voltage(0.197µm2).

JJ1-8: First Demonstration of a Full 28nm High-k/Metal Gate Circuit Transfer from Bulk to UTBB FDSOI Technology Through Hybrid Integration, D. Golanski et al, ST Microelectronics and CEA-LETI

For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame of our hybrid technology. Competitive ESD performance for the same footprint is achieved through hybrid MOSFETS snap-back voltage reduction, obtained by implant engineering. In addition, we demonstrate that the performance of Silicon Controlled Rectifier (SCR) and ESD diodes are matched vs Bulk technology while maintaining the performance of FDSOI devices and without any additional masks.

JJ1-9: 2.6GHz Ultra-Wide Voltage Range Energy Efficient Dual A9 in 28nm UTBB FD-SOI, D. Jacquet et al. STMicroelectronics

This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to 1.2V, and forward body bias (FBB) techniques up to 1.3V bias voltage, thus enabling an extremely energy efficient implementation.
(Note: ST has indicated that 2.6GHz voltage range in the title dates from the time the paper was submitted earlier this year; the actual presentation will show a more extended range.)

JJ2-1 (Invited): Fully-Depleted Planar Technologies and Static RAM, T. Hook et al, IBM, STMicroelectronics, LETI

Key elements of FDSOI (Fully Depleted Silicon on Insulator) technology as applied to SRAMs are described.Thick- and thin-Bottom Oxide (BOX) variants are discussed.

JJ2-4: Ultralow-Voltage Operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM Down to 0.37 V Utilizing Adaptive Back Bias, Y. Yamamoto et al, Low-power Electronics Association & Project (LEAP), The University of Tokyo

We demonstrated record 0.37 V minimum operation voltage (Vmin) of 2Mbit Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to small variability of SOTB (AVT~1.2-1.3 mVμm) and adaptive body biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
(Note: SOTB is a flavor of planar FD-SOI.)

In the Circuits Symposia

Paper T2-2: High Performance Si1-xGex Channel on Insulator Trigate PFETs Featuring an Implant- Free Process and Aggressively-Scaled Fin and Gate Dimensions, P. Hasemi et al., IBM & GlobalFoundries.

The adoption of advanced high-mobility Silicon Germanium (SiGe) channel materials with aggressively scaled Tri-gate pFETs on insulator is reported for the first time. SiGe is widely known as a suitable channel material for p-type MOS device, thanks to its higher hole mobility than that in conventional silicon material. In this paper, IBM and GlobalFoundries report a SiGe channel Tri-gate pFET with aggressively scaled Fin width (Wfin) and Gate length(Lg) dimensions, which is fabricated using SiGe on insulator substrate. Excellent electrostatic control down to Lg= 18 nm and Wfin< 18 nm has been reported. Using an optimized implant-free raised source/drain process, on-current Ion = 1.1 mA/µm at off-leakage current Ioff = 100 nA/µm and supply voltage Vdd= 1.0 V has been achieved.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm. (b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

(a) Cross-section TEM images across SiGe fin with Hfin = 17 nm and Wfin = 10.0, 13.5 and 18.0 nm.
(b) Cross-section TEM image of a single-fin with Gate length less than 20 nm.

15-4: A 28GHz Hybrid PLL in 32nm SOI CMOS, M. Ferriss et al, IBM

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140μmx160μm 32μm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.

21-1: A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS, L. Kull et al, IBM, EPFL

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate selection clocking scheme for time skew minimization and per-channel gain control based on low-power reference voltage buffers. Gain control of each sub-ADC is based on a fine-grain, robust R-3R ladder. The sub-ADC stacks the capacitive SAR DAC with the reference capacitor to reduce the area and enhance the settling speed. The speed and area optimized sub-ADC as well as a short tracking window of 1/8 period enable a low input capacitance and therefore render an input buffer unnecessary. The ADC achieves 38.5dB SNDR and 58fJ/conversion-step with a core chip area of 0.025mm2in 32nm CMOS SOI technology.

21-3: An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI, V.H.-C. Chen and L. Pileggi, Carnegie Mellon University

This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FoM of 59.4fJ/conv-step.

In the Technology Symposia

5-3: Optimal Device Architecture and Hetero-Integration Scheme for III-V CMOS, Z. Yuan et al, Stanford University, Applied Materials, Sematech, Texas State University

Low density-of-states (DOS) of carriers and higher dielectric constants in III-Vs warrants transistor architecture with better electrostatics than conventional FinFETs. Additionally, the integration of III-V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III-Vs and silicon. This paper presents a statistical variability study of III-V and Si FinFETs, from which SOI-FinFET architecture is recommended for III-Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.

10-1: Benefits of Segmented Si/SiGe p-Channel MOSFETs for Analog/RF Applications, N. Xu et al, University of California, Applied Materials, Soitec

Segmented-channel Si and SiGe P-MOSFETs (SegFETs) are compared against control devices fabricated using the same process but starting with non-corrugated substrates, with respect to key analog/RF performance metrics. SegFETs are found to have significant benefits due to their enhanced electrostatic integrity, lower series resistance and greater mobility enhancement, and hence show promise for future System-on-Chip applications.

14.5: 64nm Pitch Interconnects: Optimized for Designability, Manufacturability and Extendibility, C. Goldberg et al, STMicroelectronics, Samsung Electronics, GlobalFoundries, IBM

In this paper, we present a 64nm pitch integration and materials strategy to enable aggressive groundrules and extendibility for multi-node insertions. Exploitation of brightfield entitlements at trench and via lithography enables tight via and bi-directional trench pitch. Setting the same mask metal spacing equal to CPP maximized density scaling and speed of standard cell automation by avoiding cell abutment conflicts. A Self-Aligned-Via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask. Yield ramp rate, groundrule validation, and reliability qualification were each accelerated by early brightfield adoption for trench and via, producing a robust cross-module process window. The resulting groundrules and process module have been plugged in to multiple technology nodes without re-development needed (e.g. 20LPM, 14nm FINFET, 14FDSOI, 10nm P&R levels). Scaling, performance, and reliability requirements are achieved across a spectrum of low power-high performance applications.

15-1: Innovative Through-Si 3D Lithography for Ultimate Self-Aligned Planar Double-Gate and Gate-All-Around Nanowire Transistors, R. Coquand et al, STMicroelectronics, CEA-LETI, IMEP-LAHC

This paper reports the first electrical results of self-aligned multigate devices based on an innovative 3D-lithography process. HSQ resist exposition through the Silicon channel allows the formation of self-aligned trenches in a single step. Planar Double-Gate (DG) and Gate-All-Around Silicon Nanowire (GAA Si NW) transistors are fabricated with conformal SiO2-Poly-Si gate stack and the first electrical results obtained with this technique are presented. The good nMOS performances (ION of 1mA per μm at VT+0.7V) with excellent electrostatics (SS down to 62mV per dec and DIBL below 10mV per V at LG 80nm) are paving the way to the ultimate CMOS architecture. To meet all requirements of lowpower SoCs, we also demonstrate the feasibility of fabricating such devices with High-K Metal-Gate (HK-MG) stack and their possible co-integration with FDSOI structures.

15-3: Scaling of Ω-Gate SOI Nanowire N- and P-FET Down to 10nm Gate Length: Size- and Orientation-Dependent Strain Effects, S. Barraud et al, CEA-LETI, CEA-INAC, STMicroelectronics, IMEP-LAHC

High-performance strained Silicon-On-Insulator nanowires with gate width and length scaled down to 10nm are presented. For the first time, effectiveness of sSOI substrates is demonstrated for ultra-scaled N-FET NW (LG=10nm) with an outstanding ION current and an excellent electrostatic immunity (DIBL=82mV/V). P-FET NW performance enhancement is achieved using in-situ etching and selective epitaxial growth of boron-doped SiGe for the formation of recessed Sources/ Drains (S/D). We show an ION improvement up to +100% induced by recessed SiGe S/D for LG=13nm P-FET NW. Finally, size- and orientation-dependent strain impact on short channel performances is discussed. <110> Si NWs provide the best opportunities for strain engineering.

17-2 (Late News): Experimental Analysis and Modeling of Self Heating Effect in Dielectric Isolated Planar and Fin Devices, S. Lee et al, IBM

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.