Tag Archive Synopsys

CMP delivers multi-project wafer runs of 28nm FD-SOI with impressive device performance

CMPmultiwaferCMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. 
In 2013, they had 32 prototypes from 15 customers over three runs. The latest run embedded 25 different projects. Delivery of that run to users will be in Q2 2014.

“We have a total of 140 institutions/companies already using the PDK. Four MPW runs are scheduled in 2014, one for each quarter,” said Dr. Torki. MPW price is 15000 Euro/mm2.

“At CMP we fully support UTSOI model cards available in the process design-kit (PDK) for the 28nm FDSOI process,” explains Dr. Torki. The simulation model itself is available for Eldo, Spectre and Hspice. Cadence, Mentor and Synopsys make this model available as a standard feature thanks to a Leti-ST licensing agreement.

Look for news about availability of Leti’s new UTSOI2 model (click here for more information on the model) for 14nm FD-SOI in Q2.

The FD-SOI Papers at IEDM ’13

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.

Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.

9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries) 

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

ST_IEDM13table1
[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012

 

Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 

ST_IEDM13_Fig4

and below.

The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”

 

7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.

 

20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.

 

12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.

 

33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.

 

2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.

 

5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (Tw) than predicted by the T6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.

What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafersWhat you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.

The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.

The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2.  At this point in scaling, that gets you about two million gates – about eight million transistors.  So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.

Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.

Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.

The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.

CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.

The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.

CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.

How it works

In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:

  • NDA processing
  • the design-kits linking CAD and processes, and related support
  • Design submission, checking, and final database to the Fab
  • Wafer sawing and Packaging
  • Export license processing
  • Chip delivery

Because reticles are shared across multiple designs, CMP customers benefit from very attractive pricing. (Courtesy: CMP)

Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.

For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.

These are real, leading edge chips and circuits we’re talking about. Here’s what you get:

  • 28nm HK/MG FD-SOI with ultra-thin BOX and ground plane
  • 10 Cu metal layers: (6 thin + 2 medium + 2 thick)
  • Triple Well (Deep N-Well allows the P-Well to be isolated from the substrate)
  • Single IO oxide + Single core oxide.
  • Double VT: 1.0V Low Vt transistors (LVT) + 1.0V super Regular Vt transistors (RVT)
  • Low Leakage (high density) SRAM using LP core oxide
  • IO supply voltage: 1.8 V using the IO oxide.
  • Ultra Low k inter-level dielectric
  • 0.10µ metal pitch
  • Self-aligned silicided drain, source and gate
  • Poly and active resistors: Silicide protection over active areas for ESD protection
  • CMP for enhanced planarization (on STI, Contacts, Metals and vias).

FD-SOI Transistor (Courtesy: ST)

The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:

  • CORE_LL: Low Power LVT
  • CORE_LR: Low Power RVT
  • CLOCK (LL and LR): Buffer cells and the same for clock tree synthesis
  • PR: Place and route filler cells.

The IO cells Libraries include:

  • Digital
  • Analog
  • Flip-Chip bumps
  • ESD

You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.

So this represents a real opportunity.  Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.

FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip.  Wouldn’t you like to give it a try?

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

Meritage Resort and Spa in Napa Valley

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)

The papers

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. FullyDepleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: FullyDepleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

The courses & panel

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

Power & Performance: GSS Sees SOI Advantages for FinFETS

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.

To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.

The GSS IEDM ’11 Paper

GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks.  The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.

At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones.  Then they also need to provide reliable models to designers who will use them before committing chips to silicon.  One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.

At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs.  This covered  “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”.  Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.

That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project.  It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:

  • A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”.  Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
  • The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.

The Blogs

A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE TimesElectronics Weekly and EDN.  For reference, here are the blogs and basically what they concluded:

Specifically, the July 27th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better.  Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).

The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”.  GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.

Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current.  But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.

Next project

IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitledFins on transistors change processor power and performance”.

Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”

The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.

From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec):

“ FD-SOI Executive Summary

Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too.

At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors.

Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer.

Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments. ”

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

ST Technology Overview

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section):

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    – further improved electrostatic control and relaxed thinness requirement of the top silicon,

    – enables back-biasing through the BOX,

    – enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    – brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that

the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)


Excellent
speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)


Focus on SRAM: 
The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline


SPICE
Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

Perspectives

28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.

Low Power Design: Fast & Green

SOI helps create faster chips that consume less power.

Speed and area used to be the primary factors considered by chip designers. Performance requirements were established, and the power consumption required to achieve them was just another detail. In recent years, chip designers hit a wall. And sustainability moved to the forefront of industry.

Achieving higher chip speeds demanded increased power, but chips ran too hot for conventional cooling methods and drew exorbitant amounts of energy. An advanced technology known as SOI now makes new levels of chip performance and efficiency possible. SOI allows chip designers to create faster chips that are “greener” by using less power. Read More

Chip Designers: Having It All

With SOI, the performance-power trade-off can be balanced without changing design methodology.

If you’re a chip designer, what would it mean if you could measurably increase performance while keeping the same power consumption? Or, if you could meaningfully lower power consumption while retaining the same performance level? And what if you could do either one without changing methodology?

You might be really surprised. Read More

Partners In Design: Standard Tools Simplify Rad-Hard SOI Design

Honeywell has worked with the top EDA tool vendors to develop the SOI process design kits (PDKs) needed by both in-house designers and foundry customers. Rick Veres, Honeywell EDA Manager, explains.

ASIC Design With Pilot Flow

For digital rad-hard ASIC design, we worked with Synopsys to adapt the Pilot Design Environment to our process. The environment supports their entire RTL to GDSII flow, including all their synthesis tools, place and route, insertion and so forth—the standard industry flow. Our SOI cell libraries are all radhard optimized for commercial, military or satellite applications.

Analog, Mixed Signal, RF and High Temp

Honeywell provides mixed signal/analog SOI devices and cells to support a broad range of customer’s mixed mode ASICs. The design environment maintains all the digital capabilities while supplying analog cells and SRAM for true mixed signal ASICs. The design flow and associated Design Kits are supported for Cadence mixed signal tools.

For RFIC design and simulation, Honeywell’s SOI fab processes are supported by Cadence (Tality) PDKs, including RF Spectre.

For high temperature SOI CMOS, the Cadence PDK full-custom development library supports Cadence schematic capture, simulation, layout and verification tools.

Calibre for Physical Verification

Mentor Graphics has been very instrumental in helping us develop our SOI capability in their Calibre tool. We use Calibre to verify designs before we run them in the fab. There are some nuances that a user doesn’t see, that as a developer we do. For example, we have twice as many rules we have to implement and check in SOI versus standard bulk. But the complexity is all on the developer side. The user just runs it—it’s transparent to them. Mentor Graphics has done some significant and impressive work for us.