Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.
This year’s program includes:
The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.
Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris
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Find all the details about the conference on our website: s3sconference
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The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928
October 5th thru 8th, 2015
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By Ali Khakifirooz (Spansion)
One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward body bias (FBB) is available owing to oxide isolation and the use of flip-well structure .
While designers are familiar with the concept of body biasing and have been using it in different forms for many years in bulk CMOS technology, concerns are occasionally raised – often from non-designers – about the complexity and effectiveness of body biasing in advanced nodes.
Body biasing has been known for many years  and was in fact identified as a key technology enabler in sub-0.1µm era by industry leaders . Although ironically the recent move to the FinFET structure removed this gadget from the designers’ toolbox, the need for body biasing is still echoed .
Early studies demonstrated the effectiveness of body biasing in reducing leakage, improving performance, and reducing variability and thereby worst-case power consumption in complex circuits [5-7]. It was, however, pointed out that due to the competing effect of other leakage mechanisms, such as band-to-band tunneling, the effectiveness of reverse body bias (RBB) in managing leakage diminishes with technology scaling . Nonetheless Intel continued using body biasing at least down to 45nm node .
Static Body Biasing
Device variability is one of the key detractors of product yield. Historically, the desktop-driven semiconductor industry used product binning to turn this natural performance variability into profit. However, it is known that changes in market demand or process may lead to significant imbalance between the demand and inventory . Moreover, with the emergence of mobile applications as the dominant technology driver  and strict power requirements, binning is not effective anymore. With the desire to reduce VDD below 0.8V in order to reduce active power, managing the device variability becomes increasingly important.
Body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.
For example, in a media processor design in 65nm technology a 20% reduction in the worst-case delay was achieved by using an embedded FBB circuit . While most body biasing designs are geared toward keeping VT constant, it has been shown that a combination of VT and drive current control leads to significantly tighter distribution (an 85% reduction in variation) and 25% reduction in total power . These numbers are well comparable to the power saving expected from scaling the design by one technology node. Given the concerns about the saturation of cost scaling beyond 28nm, an FD-SOI design with a wide range of body biasing is thus very appealing.
Dynamic Body Biasing
For applications with varied workload, a more elaborate use of body bias is to adjust the transistor performance based on the workload. This can be, of course, combined with other known low-power techniques such as dynamic voltage and frequency scaling (DVFS), sleep transistors, power gating, etc. In particular, when combined with DVFS, the optimum VT for each VDD can be used to minimize total power .
Design Complexity and Area Overhead
Potentially added design complexity and area overhead due to body bias generation circuits and routing is sometimes voiced as a concern. Static body biasing is relatively easy to implement. Depending on the level of sophistication it requires some sensing circuits (leakage, delay, skew, temperature, etc.), charge pump circuits to generate the body bias, and a network to distribute it across the chip. In typical designs, this does not impose more than 1-2% area overhead. The design complexity is actually reduced as less resources are needed to meet target performance across process and temperature corners. Notable bulk CMOS designs that used body bias to reduce variability include Samsung’s ExynosTM SoC in both 32nm and 28nm node [13-14], and Oracle’s SPARC processors in 40nm .
Dynamic body biasing, on the other hand, needs additional system and software development. However, we do not expect this to be more complex than implementing any other low-power technique such as dynamic voltage scaling. An example is TI’s 45nm OMAP SoC that used body bias as a part of their SmartReflex technology (Figure 1) .
Figure 1. Example of combined dynamic body bias and voltage scaling in TI’s 45nm SoC . Proper VDD and body bias is selected based on the power mode and process corner. (Courtesy: ISSCC, TI)
No Body Effect?
While many bulk CMOS designs used body bias in some form, on the other end of the spectrum are the designs that used PD-SOI technology, where majority of the devices do not have a body contact. The lack of body effect in PD-SOI devices was claimed to help stacked transistors and passgates, leading to 15-25% speed improvement . For designers that prefer a zero-body-effect style, the move to FinFET or a thick BOX FD-SOI structure seems more natural. However, for mainstream applications where power and parametric yield are the main drivers, thin BOX FD-SOI and use of body bias is more sensible.
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 D. Jacquet, et al., “A 3 GHz dual core processor ARM CortexTM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization,” IEEE JSSC, p. 812, 2014.
 M. Kube, R. Hori, O. Minato, and K. Sato, “A threshold voltage controlling circuit for short channel MOS integrated circuits,” ISSCC, p. 54, 1976.
 S. Thompson, I. Young, J. Greason, and M. Bohr, “Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 µm logic designs,” Symp. VLSI Tech., p. 69, 1997.
 G. Yeap, “Smart mobile SoCs driving the semiconductor industry: technology trend, challenges and opportunities,” IEDM Tech. Dig., p. 1.3.1, 2013.
 M. Miyazaki, et al., “A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias,” ISSCC, p. 420, 2000.
 S. Narendra, et al., “1.1V 1GHz communication router with on-chip body bias in 150nm CMOS,” ISSCC, p. 218, 2002.
 J. Tchanz, et al., “Adaptive body bias for reducing impact of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” ISSCC, p. 422, 2002.
 A. Keshavarzi, et al., “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s,” ISLPED, p. 252, 1999.
 F. Hamzaoglu, et al., A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal-gate CMOS technology,” ISSCC, p. 376, 2008.
 J.Y. Chen, “GPU technology trends and future requirements,” IEDM Tech. Dig., p. 3, 2009.
 S. Nomura, et al., “A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology,” ISSCC, p. 262, 2008.
 M. Sumita, et al., “Mixed body-bias technique with fixed Vt and Ids generation circuits,” ISSCC, p. 158, 2004.
 S.-H. Yang, et al., “A 32nm high-k metal gate application processor with GHz multi-core CPU,” ISSCC, p. 214, 2012.
 Y. Shin, et al., “28nm high-k metal-gate heterogeneous quad-core CPUs for high-performance and energy efficient mobile application processor,” ISSCC, p. 154, 2013.
 J.L. Shin, et al., “A 40nm 16-core 128-thread CMT SPARC SoC processor,” ISSCC, p. 98, 2010.
 G. Gammie, et al., “A 45nm 3.5G baseband-and-multimedia application processor sing adaptive body-bias and ultra-low-power techniques, ISSCC, p. 258, 2008.
 M. Canada, et al., “A 580MHz RISC microprocessor in SOI,” ISSCC, p. 430, 1999.
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The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.
Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.
This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.
The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.
(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)
ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.
Here’s a rundown of the sessions:
Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.
The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.
Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.
All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?
With scaling, SRAM design rules are far tighter than logic. New device structures may be needed.
6T SRAMs are the backbone of embedded CMOS memory. Today SRAMs occupy over 50% of the total chip area. The SRAM cell sizes have been shrinking by ~50% each node. Such aggressive scaling has pushed SRAM design rules far tighter than logic. Read More
In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar CMOS transistors that improve performance and minimize current leakage •
The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness).
The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors (planar & non-planar), ESD structures, Kelvin structures and various test circuits (Ring Oscillators, loaded gates, Current Mirrors, OP-AMPs, SRAM cells, and reliability test sites). Read More