Toshiba has announced TaRF8, the next generation in the company’s TarfSOI™ (aka Toshiba advanced RF SOI) process, which is optimized for RF switch apps. The first product to use the technology is Toshiba’s new SP12T, enabling the lowest-class of insertion loss in the industry. Lowering insertion loss is recognized as particularly important in decreasing RF transmission power loss, which in turn means longer battery life for mobile devices. Sample shipments of SP12T RF switch ICs fabricated with the new process will start in January 2016. (See the press release here.)
Designed for use in smartphones, the SP12T RF switch is suitable for 3GPP™ GSM, UMTS, W-CDMA, LTE™ and LTE-Advanced standards.
Toshiba develops high-performance RF switch ICs using its in-house fab’s SOI-CMOS technology, which is suitable for integrating analog and digital circuits. By handling all aspects of production flow, from RF process technology development to the design and manufacturing of RF switch chips, Toshiba says it can quickly improve SOI-CMOS process technology in response to feedback from the development results of its own RF switch IC products. This IDM approach allows Toshiba to rapidly establish new process technologies suited to actual products, and to enter the market with products fabricated with the latest process technology.
As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.
But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year. In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.
The RF-SOI Juggernaut
SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.
In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.
In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.
In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.
In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications. Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.
14nm SOI-FinFETs Get Real
In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs. SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)
They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.
For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.
Representative bulk-based (junction-isolated) and SOI-based (dielectric-isolated) fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET. (Courtesy: IBM)
Manufacturing a FinFET on SOI also enables a more ideal fin profile. In turn, this near-ideal shape delivers performance well in line with the “theoretical” benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.
IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.
The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.
So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!
Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size.
The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The new TaRF5 process delivers approximately 25% lower insertion loss (at 2.7 GHz) and approximately 40% size reduction (for SP10T), compared to the comparable devices fabricated with the TaRF3 process.
Sample shipments of the SP10T (which stands for Single Pole Ten Throw Switch) have now started.
The TarfSOI™ process was first developed in 2009. The SOI advantage, says Toshiba, is the insulating film under the channel of the MOSFET, reducing stray capacity to improve speed and power saving of the CMOS LSI. The latest improvements can lead to longer battery operating time and smaller mounting space, which can also contribute to smaller sizes for products in which they are used, says the company.
Since the first TarfSOI generation, Toshiba has been continually developing new generation processes and devices offering improved performance. The company explains that RF antenna switch requirements for the current LTE and next-gen LTE-Advanced are leaning towards multi-port and complex functions. That’s why, to meet those market demands, Toshiba plans to continue to develop products with low insertion loss and smaller sizes.
SOI for front-end RF solutions is rapidly gaining ground throughout the industry. In recent months, announcements have been made by Peregine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement recently found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth. Who’s next?
The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.
Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.
This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.
The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.
(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)
ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.
Here’s a rundown of the sessions:
Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.
The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.
Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.
All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?
It’s on SOI. Here’s Why.
Toshiba’s new Cell Regza TV is poised to redefine both high-definition (HD) TV and TV-Internet convergence. At the heart of this strategy is the SOI-based Cell processor.
It was almost a decade ago when Toshiba first teamed with IBM and Sony to create the Cell. The SOI-based solution enabled the right balance of maximal performance in a minimal power envelope. IBM puts it in servers, and Sony in the PlayStation3™. Now, Toshiba has put it at the heart of its new flagship Regza. Read More
Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More