Tag Archive Toshiba

Toshiba announces new RF-SOI process and smartphone switch with industry-best insertion loss

Toshiba has announced TaRF8, the next generation in the company’s TarfSOI™ (aka Toshiba advanced RF SOI) process, which is optimized for RF switch apps. The first product to use the technology is Toshiba’s new SP12T, enabling the lowest-class of insertion loss in the industry. Lowering insertion loss is recognized as particularly important in decreasing RF transmission power loss, which in turn means longer battery life for mobile devices. Sample shipments of SP12T RF switch ICs fabricated with the new process will start in January 2016. (See the press release here.)

Designed for use in smartphones, the SP12T RF switch is suitable for 3GPP™ GSM, UMTS, W-CDMA, LTE™ and LTE-Advanced standards.

Toshiba develops high-performance RF switch ICs using its in-house fab’s SOI-CMOS technology, which is suitable for integrating analog and digital circuits. By handling all aspects of production flow, from RF process technology development to the design and manufacturing of RF switch chips, Toshiba says it can quickly improve SOI-CMOS process technology in response to feedback from the development results of its own RF switch IC products. This IDM approach allows Toshiba to rapidly establish new process technologies suited to actual products, and to enter the market with products fabricated with the latest process technology.

The SOI Papers at VLSI ’14 (Part 2):

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!

 

(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.

 

4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.

 

6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.

 

8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalon et al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.

 

9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.

 

13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

 

13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

 

17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

 

18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.

 

18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.

 

18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.

 

SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.

 

UTwenteC194VLSI14lowres

(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)

 

 

C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

SOI: Looking Back Over a Year of Moving Forward (Part 2, RF-SOI & SOI-FinFETs)

As we noted in the previous post (click here if you missed it), 2014 should be a terrific year for the greater SOI community.

But before we look forward (which we’ll do in an upcoming post), let’s continue considering where we’ve been and some of the highlights of the last year.  In fact, there was so much happening in 2013 that it’s taken two posts – the previous was about FD-SOI; in this post we’ll review RF-SOI and SOI-FinFETs.

 

The RF-SOI Juggernaut

SOI for front-end RF solutions rapidly gained ground throughout the industry in 2013, with announcements by Peregrine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth.

In April, SemiconductorEngineering reported that part of Qualcomm’s RF360 front-end solution is on SOI, a “shot across the bow”, according to StrategyAnalytics.

In June, ST announced a new manufacturing process, known as H9SOI_FEM, for production of complete integrated front-end modules.

In October, Toshiba chimed in with a new RF-SOI product announcement, noting that it had been using SOI for RF since 2009.

Peregrine_ultracmos_waferLoRes

(Photo: Business Wire)

In November, Peregrine Semiconductor announced that it has shipped its 2 billionth RF chip, released version 10 of its UltraCMOS RF-SOI technology, and is working with GlobalFoundries.

 

 

 

eSI_SoitecUCLwafer

A new generation of HR-SOI substrate:
enhanced Signal Integrity™ (eSI)
(Image courtesy of Soitec)

In December, SOI wafer leader Soitec announced that they’re in high-volume manufacturing of a new flavor of SOI wafers for advanced RF apps like LTE/4G. In fact, these new wafers are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications.  Developed with UCL, they’re called Enhanced Signal Integrity™ (eSI) substrates, and enable cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production.

 

 

14nm SOI-FinFETs Get Real

In November, IBM posted a piece in ASN entitled FinFET on SOI: Potential BecomesReality. The IBM team shared impressive hardware data for 14nm SOI-FinFETs.  SOI eliminates the need for doping, they remind us, which enables FinFETs to attain unsurpassed threshold voltage (Vt) matching between transistor pairs. (Vt is the point at which a transistor switches on or off.)

They found, on top of the well-documented improvements in Vt matching for logic and SRAM devices, an even more dramatic matching improvement for thick-dielectric devices. These are used for analog and IO devices, and also in DRAM — where this opens the door to various optimizations and enables fundamental area scaling.

For the classic 6T SRAM, improved Vt matching means you can lower the minimum operating voltage. For their SRAM array, the IBM team showed minimum operating voltage down to 400mV, with full read and write capability. That’s as good or better than any yet reported, and it was done without using chip-specific tuning techniques. The bottom line: real SOI-FinFET SRAMs can operate at very low voltages.

ASN_IBM_SOI_FinFET

Representative bulk-based (junction-isolated) and SOI-based (dielectric-isolated) fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET. (Courtesy: IBM)

 

 

Manufacturing a FinFET on SOI also enables a more ideal fin profile.  In turn, this near-ideal shape delivers performance well in line with the “theoretical”  benefits of FinFET technology. It avoids the need for the more tapered shape seen on bulk FinFETs that trade-off some electrical performance for manufacturability.

IBM’s results exhibit excellent correspondence between the actual hardware and the expectations, which include far less dependence on the supply voltage than conventional planar technology.

The various pieces contributed to ASN by IBM about SOI-FinFETs are amongst our all-time most popular posts. We’ve also shared some of them with the folks over at SemiMD, where they continue to generate enormous interest.

So we’ll look forward to hearing more about SOI-FinFETs in 2014, too!

Toshiba Says New RF-SOI Antenna Switch for Smartphones Is Smallest

Another RF-SOI solution is making headlines. Leveraging SOI, Toshiba has announced an SP10T RF antenna switch for the smartphone market. The company says it achieves the industry’s lowest insertion loss and smallest size.

The company credits its new generation TaRF5 process, the latest in its line of Toshiba-original TarfSOI™ (Toshiba advanced RF SOI) processes. The new TaRF5 process delivers approximately 25% lower insertion loss (at 2.7 GHz) and approximately 40% size reduction (for SP10T), compared to the comparable devices fabricated with the TaRF3 process.

TOSHIBA_SP10T_INSERTIONLOSS_131007_

Insertion loss on Toshiba SP10T RF antenna switches (Graphic: Business Wire)

Sample shipments of the SP10T (which stands for Single Pole Ten Throw Switch) have now started.

The TarfSOI™ process was first developed in 2009. The SOI advantage, says Toshiba, is the insulating film under the channel of the MOSFET, reducing stray capacity to improve speed and power saving of the CMOS LSI. The latest improvements can lead to longer battery operating time and smaller mounting space, which can also contribute to smaller sizes for products in which they are used, says the company.

Since the first TarfSOI generation, Toshiba has been continually developing new generation processes and devices offering improved performance. The company explains that RF antenna switch requirements for the current LTE and next-gen LTE-Advanced are leaning towards multi-port and complex functions. That’s why, to meet those market demands, Toshiba plans to continue to develop products with low insertion loss and smaller sizes.

SOI for front-end RF solutions is rapidly gaining ground throughout the industry. In recent months, announcements have been made by Peregine, Magnachip, ST, IBM, TowerJazz, Skyworks, Grace Semi and RDA in China, and more. In fact, industry research firm Yole Développement recently found that more than 65 percent of substrates used in fabricating switches for handsets are SOI based. And the SOI wafer leader Soitec has said that chips built on its SOI wafers were found in over half of the smartphones and tablets in the market worldwide. This shows the massive adoption of RF-SOI for this part of the market, which is experiencing double-digit growth. Who’s next?

 

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

Meritage Resort and Spa in Napa Valley

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)

The papers

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. FullyDepleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: FullyDepleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

The courses & panel

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

Toshiba’s Cell Regza TV

It’s on SOI. Here’s Why.

Toshiba’s new Cell Regza TV is poised to redefine both high-definition (HD) TV and TV-Internet convergence. At the heart of this strategy is the SOI-based Cell processor.

It was almost a decade ago when Toshiba first teamed with IBM and Sony to create the Cell. The SOI-based solution enabled the right balance of maximal performance in a minimal power envelope. IBM puts it in servers, and Sony in the PlayStation3™. Now, Toshiba has put it at the heart of its new flagship Regza. Read More

Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More

the Cell processor that will be produced by Toshiba for availability in 2009 will be on SOI

  • According to a spokesperson, the Cell processor that will be produced by Toshiba for availability in 2009 will be on SOI. One of the first applications is expected to be in TVs.

With SOI, the new series of energy-efficient, high-voltage intelligent power devices (HV IPD) from Toshiba America Electronic Components

Figure 3

With SOI, the new series of energy-efficient, high-voltage intelligent power devices (HV IPD) from Toshiba America Electronic Components (fig. 3). (TAEC) is >25% thinner. Target applications are DC motors in home appliances.

From AMD

From AMD (which builds all its 64-bit microprocessors on SOI):

AMD’s Quad-Core Opteron™ (Courtesy: AMD)

• The Quad-Core AMD Opteron™, billed as “the world’s most advanced x86 processor ever designed and manufactured and the first native x86 quad-core microprocessor”, is built on 65nm SOI, which the company says lowers power consumption and improves performance.

• Availability of the AMD Phenom™ triple-core processors, expected to be the world’s first desktop PC processors to integrate three cores on a single die, is slated for Q108.

• Toshiba, one of the world’s largest notebook providers, is launching three Satellite® notebook PCs based on AMD Turion™ 64 X2 dual-core mobile technology.