The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.
This year’s program includes:
The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.
Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris
Download the Advance Program
Find all the details about the conference on our website: s3sconference
Click here to go directly to the IEEE S3S Conference registration page.
Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.
The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928
October 5th thru 8th, 2015
~ ~ ~
Join the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.
The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.
The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).
Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.
The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)
The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.
sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).
An impressive hot topics session was dedicated to RF CMOS.
J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.
Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.
The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).
The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.
The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.
3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.
The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.
Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.
The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.
Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.
This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.
The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.
(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)
ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.
Here’s a rundown of the sessions:
Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.
The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.
Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.
All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?
Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)
The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.
It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.
The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.
Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.
The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)
This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.
Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.
The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.
Here’s a preview of program – you won’t want to miss it.
|7:30am||Badge pick up & On-site registration|
|8:30am||Introduction by Carlos Mazure (Soitec)|
|8:40am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Design by Philippe Flatresse (ST Microelectronics)|
|9:10am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Technology by Michel Haond (ST Microelectronics)|
|9:40am||Recent Advances in FDSOI by Bruce Doris (IBM)|
|10:30am||Library and Physical IP Porting for FDSOI by Jean-Luc Pelloie (ARM)|
|11:00am||20nm FDSOI Models by Brian Chen (Accelicon & SOI Consortium)|
|11:30am||FinFET on SOI by Terrence Hook (IBM)|
|1:00pm||Enabling Substrate Technology for a Large Volume Fully Depleted Standard by Christophe Maleville (Soitec)|
|1:30pm||Strain Options for FDSOI by Olivier Faynot (CEA – Leti)|
|2:00pm||Advanced FDSOI Design by Bora Nikolic (UC Berkeley)|
|2:20pm||Closing Remarks by Horacio Mendez (SOI Consortium)|
|2:30pm||Networking and coffee buffet|