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The IEEE S3S Conference Delivered Impressive Technical Content

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A view of the Bay from Cannery row, Monterey, CA.

The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.

The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).

Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.


Chart from A. Paul (GF) showing benefits of Fin width scaling

The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)



The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.

sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).

An impressive hot topics session was dedicated to RF CMOS.

J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.

Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.

The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).

The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.

The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.


Snapshot from Dr M. Farooq’s (IBM) presentation (3DI shortcourse)

3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.


The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.

Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.


SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

IEEE S3S conference

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa)

Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.

Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.

The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.

The complete list of posters and presentations can be seen in the technical program.

This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration.  Check the list of participants on those links, and you will see that major players in the field are joining us!

Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.

(Photo Credit: Monterey County Convention and Visitors Bureau)

(Photo Credit: Monterey County Convention and Visitors Bureau)

There will be 2 short courses this year, and 2 fundamentals classes.  Those educational tracks are available to you even if you do not register for the full conference.

On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..

Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).

On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.

You could also prefer to take the opportunity to visit the Monterey area.

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest.  The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.

To take full advantage of this outstanding event, register now!

Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.

The latest conference updates are available on the S3S website (http://S3Sconference.org).


Major paper on porting SOC designs from bulk to FD-SOI released by SOI Consortium

What are you going to do with your SOCs at 20/22nm? The options seem to boil down to just staying on bulk CMOS, or changing to FinFETs or planar, fully-depleted (FD) SOI-based CMOS.

Though some may find comfort in staying on bulk CMOS, it’s getting very complicated – and complicated get expensive fast. The FinFET option (which can be on bulk or SOI) is exciting for the longer term,but in the short term still raises significant design and manufacturing challenges. That leaves FD-SOI — which in terms of cost, performance, power and complexity is turning out to be an extremely attractive option.

You’ve probably heard that FD-SOI promises major savings in power (40%) and/or a big boost in performance (25 to 80% – depending on the Vdd and design type – over low-power bulk technology).  And a recent study found that FD-SOI will be cheaper to fab than bulk because it’s less complicated.

Perhaps also you’ve heard that designing for FD-SOI is pretty much the same as designing for planar bulk CMOS.  But what would it mean from a design perspective to actually port your existing bulk SOCs to FD-SOI?  What would the impact be? What would you have to do?

SOI Industry ConsortiumMember companies of the SOI Consortium – including ARM, Leti, UCL, IBM, GlobalFoundries and Soitec – have tackled these questions.  The Consortium just posted a major technical white paper called, “Considerations for Bulk CMOS to FD-SOI Design Porting”.

It’s a must-read for anyone working on the leading edge.

Over the next few months, here at ASN we’ll be publishing excerpts and summaries.  But to give you an idea of the magnitude of this paper, here is an overview.

The scope of the study is to examine the efforts required to port existing bulk CMOS designs to FD-SOI at the same node – so we’re comparing apples to apples, as it were. It considers both bulk-to-FD-SOI IP Porting  and full chip design porting.

With respect to the full chip design porting, it considers two potential paths:

  • the straightest possible porting from bulk to FD-SOI – ideally, no change in place-and-route, and as close as possible to keeping the same GDS with all FD-SOI-specific updates automatically handled at mask generation;
  • or, optimizing the SOC implementation to take full advantage of FD-SOI options like back-biasing.

There’s a section on the FD-SOI design specificities that need to be taken into account. It sorts out in significant detail devices and electrical characteristics that are addressed at the technology level, looks at any impacts at the designer level, and indicates what is foundry-dependent.

The meat of the document is in a section called “Impact Per Design Domain”.  Here it goes into the impact of an FD-SOI port on logic library cells, memory compilers, I/Os and ESD protections, analog & mixed-signal IP, and the choice of porting approach (fastest vs. most optimized) right down to sign-off considerations.

Those considering the “most optimized” approach will want to look at the appendices that go into great detail on back-biasing for VT shifting or tuning (more efficient than, although similar to the body-biasing used in some bulk designs), as well as “native” multi-VT.

Finally, the References section is a treasure trove, listing the most important FD-SOI papers presented at the top conferences over the past few years – including VLSI, IEDM, ISSCC, the SOI Conference and more.

Overall, the approach is technical but approachable.  Let us know what you think.


A Novel Device for Ultra-Low Power & More

Power is the biggest challenge to device scaling for digital applications. Aggressive MOSFET scaling gives rise to many critical challenges, which are typically addressed by scaling the supply voltage (VDD).

A transistor is switched on (current on: Ion) if the gate voltage (VG) is higher than the threshold voltage (VTH).  However, due to deleterious “short channel effects” (SCE) such as DIBL in deeply scaled MOSFETs, VTH typically has to be above 0.25V to escape the effects of subthreshold voltage swings.

This in turn sets a limit on the supply voltage (VDD), because you need to maintain an acceptable VDD/VTH ratio for good performance. For sub-45nm CMOS, the current level at which the transistor remains switched off (IOFF) becomes very high, and the ION/IOFF ratio reduces significantly.

The high IOFF point makes power dissipation, both dynamic and static (in standby mode for mobile devices, for example), an enormous challenge, especially for low power/low current applications.

The reduced ION/IOFF ratio is a particular problem for low stand-by power applications. When you measure and diagram the Ion/Ioff states, you want a very steep subthreshold slope, indicating that the change between on and off is quick, clear and dramatic, even at low power levels.

To overcome these problems, many good engineering solutions such as improving the device architecture, introducing materials into the channel region with superior transport properties and new gate dielectrics to reduce gate tunneling have been implemented. These techniques basically attempt to make small devices “long-channel” like.

We believe a better approach would be to exploit a new device configuration made feasible by the small dimensions and new materials.

Tunnel source SOI MOSFET

We have propsed a novel device concept, the Tunnel Source (PNPN) SOI n-MOSFET ([1]-[3]), based on the principle of band-to-band tunneling, as an alternative solution towards achieving devices with steep sub-threshold behavior. The device structure is shown in Figure 1.

Figure 1. The device structure of the novel PNPN SOI n-MOSFET.

The main feature of this fully-depleted (FD) SOI device is the concept of gate-controlled carrier injection through band-to-band tunneling at the source junction (see Figure 2).

At the International Conference on IC Design and Technology (ICICDT) in May, we presented further device simulation results, which confirm that our tunneling source SOI MOSFET is an attractive candidate for low power digital and analog operations. [4]

Figure 2. The principle of operation of the PNPN SOI n-MOSFET. • In (a), no band-to-band direct tunneling is possible even though the distance is small. The current level is small since the electrons from the p+ valence band can tunnel only to the trap states. • In (b), the tunneling width reduces and the channel conduction band goes below the p+ source valence band, providing states for the carriers to tunnel to. As a result, electrons from the p+ source valence band tunnel to empty states in the channel conduction band, creating device current. Tunneling resistance reduces as gate bias increases, and the device current is limited by drift field as in a conventional MOSFET.

The device can provide a very steep subthreshold slope (<60mv/dec at RT) and IOFF far beyond the limits of conventional devices.

The sharp swing facilitates a low IOFF, which is especially favorable for low standby and operating power applications. It does not change significantly, even at the high temperatures found in high-performance microprocessors.

The ION/IOFF ratio is improved by more than three orders of magnitude over conventional SOI.  Even with aggressive scaling, simulations indicate that the degradation in subthreshold swing and IOFF with scaling is negligible. This is particularly beneficial for low standby power and low operating power technologies.

Scaling the gate oxide thickness (TX) does not affect the source tunneling junction properties much and the dependence of ION on TOX is similar to that of a normal MOSFET. This implies that the device offers the advantage of relaxing the gate oxide scaling requirements, especially for subthreshold operation in low power applications.

Our simulation results also suggest that since SCEs are greatly suppressed, the PNPN device is extremely scalable and exhibits superior digital performance.

We conclude that the PNPN SOI n-MOSFET offers a viable solution to the challenge of stand-by and operating power reduction posed by aggressive device scaling, making it an attractive choice for ultra-scaled CMOS transistors. Furthermore, it can be realized in a vertical configuration for future 3-D integrated circuits.

[1] N. V. Girish, Ritesh Jhaveri and Jason C. S. Woo, “Tunnel Source MOSFET: A Novel High Performance Transistor”, IEEE 2004 Silicon Nanoelectronics Workshop, June 13-14, 2004, pp. 33-34.
[2] N. V. Girish, Ritesh Jhaveri and J. C. S. Woo, “Asymmetric Tunneling MOSFETs: A Novel Device Solution for Sub-100nm CMOS Technology”, International Journal of High Speed Electronics and Systems, vol. 16, no. 1, 2006, pp. 95-102.
[3] Venkatagirish N., Ritesh Jhaveri and Jason C. S. Woo, “The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor”, IEEE Transactions on Electron Devices, Vol. 55, No. 4, April 2008, pp. 1013-1019.
[4] Venkatagirish N., Ahmet Tura, Ritesh Jhaveri, Hsu-Yu Chang and Jason C. S. Woo, “The Tunnel Source MOSFET: A Novel Asymmetric Device Solution for Ultra-Low Power Applications”, to be published in 2009 IEEE International Conference on Intergrated Circuit Design and Technology, 2009.