Tag Archive ULP

ByAdele Hars

ARM Steps Up! And More Good News From Consortium’s FD-SOI Symposium in Silicon Valley

ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.

The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.

Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.

ARM Pitches In

If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.

CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.

FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF.  ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).

ARM worked with Samsung to compare libraries on 28nm bulk vs 28nm FD-SOI, and came back with these very impressive results. (Courtesy: ARM, SOI Consortium)

The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption.  Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.

In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.

NXP – New Levels in ULP

Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)

NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing.  A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP)  is heading to new levels, he says.

With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.

Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)

Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.

And Much More

Briefly, here are some more highlights.

Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings.  But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.

Dreamchip:  Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI.  One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection.  They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB).  The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.

Dreamchip is using Arteris IP for their ADAS chip in GF’s 22nm FD-SOI (Courtesy: Dreamchip, SOI Consortium)

Greenwaves:  CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros.   The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.

 

Greenwaves expects big power savings in their move to FD-SOI. (Courtesy: Greenwaves, SOI Consortium)

Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.

IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim.  FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.

The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp.  IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled:  lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.

All in all, it was another really good day for FD-SOI in Silicon Valley.

ByAdele Hars

Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.

On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.

The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)

The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.  

(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)

Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.

FDSOI Short Overview and Advantages for Analog, RF and mmW Design – Andreia Cathelin, Fellow, STMicroelectronics, France

If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.

Summary slide from Professor Andreia Cathelin’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and ST)

She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology.  Then the focus  shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing.  For each category of circuits  (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass  filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.

Unique Circuit Topologies and Back-gate Biasing Scheme for RF, Millimeter Wave and Broadband Circuit Design in FDSOI Technologies – Sorin Voinigescu, Professor, University of Toronto, Canada.

Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics.  The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.

Summary slide from Professor Sorin Voinigescu’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and U. Toronto)

Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.

Design Strategies for ULV memories in 28nm FDS-SOI – Joachim Rodrigues, Professor, Lund University, Sweden

Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.

For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.

Summary slide from Professor Joachim Rodrigues’ course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Lund U.)

Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.

Energy-Efficient Processors in 28nm FDSOI – Bora Nikolic, Professor, UC Berkeley, USA

Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Summary slide from Professor Bora Nikolic’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and UC Berkeley)

Pushing the Envelope in Mixed-Signal Design Using FD-SOI – Boris Murmann, Professor, Stanford University, USA

If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.

Summary slide from Professor Boris Murmann’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Stanford U.)

Key Info About the FD-SOI Tutorial Day

  • Event: Designing with FD-SOI Technologies
  • Where: Samsung Semiconductor’s Auditorium “Palace”, San Jose, CA
  • When: April 14th, 2017, 8am to 3pm
  • Cost: $475
  • Organizer: SOI Industry Consortium
  • Pre-registration required – click here to sign up on the SOI Consortium website.

 

By

IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

Bacchus Entry

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) will be held in Sonoma Valley, CA 5-8 October 2015. (Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.

Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.

EDS Logo PMS3015_revu_smallThe conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

sponsor-ieeeWhile paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.

Program:

Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.

Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.

There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.

Welcome to Doubletree Hotel Sonoma Wine Country

(Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about Ultra-Low Power.

During the Rump session we will debate about the What does IoT mean for semiconductor technology?

Scope of the conference:

The Committee will review papers submitted by May 18 in the three following focus areas of the conference:

 

Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.

 

Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.

 

3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.

Important dates:

Paper submission deadline: 18 May, 2015

Notification of acceptance: 07 June, 2015

Short course date: 5 October, 2015

Conference date: 5 – 8 October, 2015

More details are available on the S3S website.

ByAdministrator

ASN Celebrates a Decade of SOI News, Views and Commentary

April 2015 marks the 10-year anniversary of the first ever issue of Advanced Substrate News, aka ASN, covering news and views from the SOI ecosystem.

Wow, were we precient.

Consider some of the topics we covered in that first edition, back in April of 2005:ASN10

Not bad!

ASN was recently invited to give a talk about SOI-based applications at the Shanghai Academy of Sciences (SIMIT). Putting together a presentation of SOI-based apps from the last decade turned out to be a lot of fun – and a real eye opener.

The presentation is now posted on SlideShare (click here to see it).

It reminded me that we have a veritable treasure trove of information here, both current and historical. We count contributions from virtually every major player in the industry.

If you haven’t done so recently, I’d like to invite you to explore the ASN website. With a decade’s worth of articles, that might seem a little daunting. But on the right, you’ll see our list of Tags – if you click on “All Tags” you’ll get an alphabetical listing of every topic you could think of.

We’ve come a really long way in this decade. When Oki did their FD-SOI chip for Casio in 2005, they did it on a regular SOI wafer, and it was a breakthrough. Then the announcement by Soitec in 2010 that the company had entered industrial production of the ultra-thin SOI wafers needed for high-volume FD-SOI apps opened up a whole new horizon. (Remember that until that point, nobody believed it would be possible to produce SOI wafers with the requisite top silicon uniformity of +/- 5 Angstroms.)

Now that the ecosystem’s in place, solving the low-power/high-performance challenges of IoT cost effectively, we’re all anxiously awaiting the end of this year for announcements of those high-volume FD-SOI apps.

Consider where we are today. ST says they have 18 FD-SOI design wins as of January 2015. Synapse Design has worked on 7 projects and sees more coming in. Verisilicon has some in the pipeline. GlobalFoundries has indicated they have customers lined up. And of course with the big news last year that Samsung is offering FD-SOI on a foundry basis, they are firmly behind it. Foundries mean business. If they’re offering it, it’s because they have customers.

And then there’s the RF-SOI – what an immense success. Partners Soitec and UCL had been quietly working for years on an innovative eSI substrate solution that would solve the challenges of 4G and 5G. Then suddenly it was in every new smartphone out there, and the next-gen wafer can actually predict 5G performance.

In other SOI strongholds, things are looking very good, too. Currently there are about 800 chips per vehicle – that number is on track to reach 1000 by 2020. In smart power, SOI wafers made using Soitec’s Smart Cut technology are seeing 20% CAGR, compared to 7% for the rest of the industry.

So if you want to share our crystal ball, keep reading ASN. Join our mailing list, follow us on Twitter @followASN, join our Advanced Substrate News LinkedIn group, and look for us we gear up as AllThingsSOI on WeChat.

The beginning of 2015 has been outstanding. We’ve seen double even triple the hits to the ASN website in recent months, so people are clearly looking to learn more about SOI.

I’d like to take a moment to thank the folks at SOI-wafer leader Soitec. They have sponsored ASN since day one. And thank you, too, to all the members of the SOI Consortium, who’ve given generously of their time with unflinching support and keen insights.

In the decade since ASN’s creation, we’ve seen an ecosystem blossom. Here’s to the next decade, and the new era of high-volume, low-power, high-performance SOI-based chips.

With warm regards,

– Adele

ByGianni PRATA

Interview (Leti): How a new platform helps designers get the most out of FD-SOI for IoT, ULP

CEA-Leti Clean Room (© Pierre Jayet)

CEA-Leti Clean Room (© Pierre Jayet)

A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume. Olivier Thomas, who’s in charge of the program and Ali Erdengiz, who’s Business Development Manager for Leti explain how it works.

 

Advanced Substrate News (ASN): What exactly is Silicon Impulse? What services does it offer?

OThomas2

Olivier THOMAS is the project leader of Silicon Impulse for Leti.

Olivier Thomas (OT): Silicon Impulse provides design services from emulation to test program development and qualification (emulation, advanced building blocks and IPs access, full control design flow, industrial MPW, packaging and board, test and qualification).

So you can consider Silicon Impulse as a silicon enablement and development platform: a unique IC prototype development and production hand-off partner for companies in need of the latest low-power semiconductor technologies and heterogeneous integration solutions (FD-SOI, BEOL NVM, MEMS, 3D…). We work with a strong network of industrial partners and offer a single entry point along product maturation.

Silicon Impulse leverages Leti’s* and List’s** expertise as well as top industrial partners belonging to a global network of experts in analog, RF, digital and memory design, as well as hardware/software-integrated solutions.

CEA-Leti Clean Room (©Pierre Jayet)

 

In a nutshell, Silicon Impulse offers:

  • a pool of expertise from device to system
  • access to world-class, leading-edge technologies
  • regularly scheduled industrial multi-project wafer (MPW) shuttles
  • access to a proven supply chain
  • customized collaboration to fit partner needs

[Editor’s note: Click here to download the Silicon Impulse brochure.]

ASN: Who is it aimed at?

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz (AE): We saw that the increasing cost of leading semiconductor technologies, the level of expertise, tools and resources required to develop innovative products using such advanced processes can make it really challenging for new entrants (product and solution innovators). So CEA Leti created the Silicon Impulse initiative to help innovative companies to get their projects off the ground. We provide an advanced silicon development platform, help them develop their IC and/or subsystem and then hand it off to the production supply chain.

We did this because we see that today’s new markets are driven by a variety of applications and new players – it’s not just the big players scaling for PCs and mobiles anymore. IoT is a great opportunity for the emergence of innovations and ideas from new entrants. We’ve been getting more and more requests from partners looking to integrate the advanced technologies developed in Leti such as BEOL NVM and MEMS. They’re thinking outside of the box, so they are also interested in using 28nm FD-SOI while requesting advanced features and specific performance at low-voltage. Leti has always done technology research. Now with Silicon Impulse we provide a new service in collaboration with other industrial partners to help companies evaluate, design, prototype, and launch their products.

ASN: If FD-SOI design is so easy and so close to what designers have done in bulk, why do they need this sort of service?

Leti and List have a long history of launching innovation, as seen here in the CEA-Leti Showroom (©Pierre Jayet)

 

OT: Indeed, one can easily migrate from bulk to FD-SOI and benefit immediately from its low power/low leakage characteristics. However, we’ve seen that many of the companies that port their circuits to FD-SOI don’t exploit the full potential of the technology. Silicon Impulse leverages Leti’s strong expertise and experience in FD-SOI technology from device to Digital/RF modeling and advanced design solutions and maximizes the gains of the technology. Our competence center provides its industrial partners with quick access to information, know-how and silicon proven advanced design and architecture solutions to efficiently manage performance, power consumption and process variability. Here are some examples: PVT sensors, timing fault tracking, control theory module (i.e. algorithm to figure out the optimum energy point), fast feedback loop on the top of tailored charge pump and other blocks to back bias efficiently.

In addition, Leti’s Silicon Impulse’s expertise is not limited to designing FD-SOI IC’s. Leti brings a wealth of system knowledge and application know-how from device technology through embedded software that ensures full success and differentiation for its partners’ projects.

ASN: Why should designers consider FD-SOI?

OT: The 28nm/22nm technology nodes are seen as a long-lived technology node and a sweet spot for performance, power and cost. FD-SOI is optimized for low-voltage, low-power applications that can nevertheless need high performance.

For digital design, the extended range (+/-2V) of back biasing along with PVT sensors, timing fault tracking, theory control module and fast feedback loops controlling the back bias enable efficient process compensation and energy optimization for a wide range of applications (E. Beigne et al. ISSCC’14).

For SRAM design, the un-doped planar technology offers a large portfolio of SRAM bit-cells (High-density, Low power, High-performance) enabling very good performance over a wide voltage range. The Single P-Well bit-cell architecture combined with a wide back bias range enables both low operating voltage and fast access time. In sleep mode, the back bias can be set to minimize the bit-cell standby leakage current and the data retention voltage (O. Thomas et al. IEDM’14).

For RF design, one key aspect shown in the paper presented at ISSCC 15 is the continuous re-configurability through VT adjustment by the back-gate. The Power Amplifier discussed in the paper can pass from a high-linearity/high-efficiency state to a high power state by continuous linear tuning; something that cannot be done in other technologies. At the same time, the 28 FD-SOI allows designers reach much higher FT/Fmax than bulk. The result is higher available gain in mm Wave (as shown in our example at 60GHz). This approach drastically reduces the PA’s power consumption in 90% of the use cases, thus enabling WiGig for example in mobile applications.

ASN: What are the logistics for getting started?

OT, AE: Silicon Impulse can help innovators with their projects from concept through production hand-off. To get started on a project, we do a business review to determine where and how Silicon Impulse can contribute. We can provide architectural advice and shape the product from a very high level, develop a feasibility study and make recommendations as to how to implement the system. Leti and its partners can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, MEMS, 3D components and any other advanced technology to shape a truly unique and advanced yet manufacturable product. Another layer of contribution of Leti, List would be in providing embedded software to complete the whole product. So Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between.

Construction of an extension to the Minatec campus is now underway, which will be the new home to Leti’s Silicon Impulse® service. (Architect’s rendering of the IC Design Competence Center building, north view shown here, ©Futur A Architectes)

 

ASN: You’re running multi-project wafer (MPW) shuttles – can you tell us more about that?

OT: Leti offers its MPW shuttles to open the doors to a wider set of users and projects (some of whom might not have access to or be ready yet for full service foundries). An MPW shuttle serves two main purposes:

  • Enable innovators to test their ideas, especially mixed-signal, analog or RF or any new IP that would require silicon validation in FD-SOI
  • Provide an affordable platform for startups and other small companies to build their prototypes and run small volumes until they can raise enough funds and/or demonstrate market traction to build their own mask set.

However, we’ll also be making an announcement in the near future with details of schedules for planned MPW shuttles with our industrial partners.

ASN: How long will it take to get to a working design?

AE: This is project dependent, but leveraging Leti’s experience and already proven IPs and methodologies it is likely that our partners will develop a successful design even faster than if they did it on their own regardless of whether they used FD-SOI or bulk. Using FD-SOI for digital design targeting low power without compromising performance will certainly get you there faster than using bulk. In addition, the intrinsic characteristics of FD-SOI and much better control of device variability will accelerate analog and RF design and reduce time to market.

ASN: Will the design then be transferable to a full-service, high-volume fab?

OT: The purpose of Silicon Impulse is to ease IC prototype development and enable/accelerate production ramp-up. Silicon Impulse completes the Leti R&D offering by transferring the technology into a manufacturable product. The production is then handed off to a full service fab and/or supply chain partner. We’ll begin announcing the names of these partners shortly.

For information on contacting Leti’s Silicon Impulse service, click here.

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Olivier THOMAS is the project leader of Silicon Impulse for Leti. He received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti’s advanced memory design activity. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

Ali Erdengiz is Business Development Manager for Leti/List. He has spent 20 years in Silicon Valley and held various engineering, marketing, product and business unit management functions at companies such as ST Micro, National Semiconductor, Fujitsu, Altera, Abound Logic and eSilicon. Ali holds a BSEE from ESME, an MSEE from Université Parix XI and an MBA from San Jose State University.

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Minatec_aerial_lores

Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

*CEA-Leti is a research-and-technology organization with a large and word class expertise from device through system integration. It specializes in nanotechnologies and their applications. NEMS and MEMS are also at the core of its activities. Leti is capable of not only developing semiconductor devices (analog, mixed-signal, RF, digital, MEMS) but also integrating them into subsystems using PCB, MCM, 2.5D and 3D technologies as well as developing embedded and application software to deliver full system level solutions.

 

**A sister organization to CEA-Leti, CEA-List conducts R&D in fields that create value for the economy and society. As such, the primary mission is to give businesses the tools they need to turn their innovative ideas into marketable products.

 

ByGianni PRATA

Samsung/ChipEstimate video gives strong plug for FD-SOI

In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). While the first half addresses 14nm FinFET, starting at the 2:25 mark, it’s all about FD-SOI.

SamsungCDN

Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI in a CDNLive interview with ChipEstimate.TV’s Sean O’Kane.

First Kelvin reminds viewers that 28nm will be a long-lived node thanks to its lower costs and the fact that it doesn’t use double patterning. He says Samsung has acquired a number of customers for FD-SOI, and now has the complete ecosystem to support the process technology, from substrate suppliers through the design chain. The key value, he says, is in the extremely low power operation and the low power supply voltage, which translates into long battery life for IoT and wearables. He also says he’s very excited by the prospects for FD-SOI in the automotive domain, where it is especially valued for its enhanced reliability.