Tag Archive ultra-low-power

QuickLogic ultra-low power eFPGA on GF’s 22FDX FD-SOI and in PULP/RISC-V SoC

(Courtesy: PRNewsfoto/QuickLogic Corporation)

Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now.

ArcticPro is the industry’s first eFPGA offering for GF’s 22FDX® process (btw they’ve been shipping it in volume for GF’s 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device’s functionality in the field.

(Image courtesy: QuickLogic)

QuickLogic has also announced that the technical university ETH Zurich  will integrate QuickLogic’s ArcticPro technology onto the university’s PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF’s 22FDX process node. They will develop an SoC integrating ETHZ’s open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption.

“The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” said QuickLogic CTO Dr. Timothy Saxe. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”

ETH’s PULP platform with the fully integrated eFPGA is expected to be available Q1′ 2019.

QuickLogic is part of GF’s fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.

How FD-SOI Gives NXP’s i.MX7ULP a “Power-Sipping IoT Budget” (Embedded Systems Engineering)

Here’s why the embedded community should care whether the chips they use are built on FD-SOI. FD-SOI has “…dramatically improved the landscape for power efficiency,” NXP VP Joe Yu explains in a recent Embedded Systems Engineering piece (you can read it here). He gets into the hows and whys of the i.MX7ULP chip design, taking a deep dive into the things that the embedded folks really care about.

He details how FD-SOI decreases leakage and dynamic power, including the roles played by forward and reverse body biasing. He then goes on to explain why it’s better for analog, and how it prevents latch-up.

FD-SOI enables new features, too, he points out, like ultra-low power consumption and deep sleep suspend. And perhaps most importantly, he explains how bursty high-performance and ultra energy efficiency are dynamically traded off on an as-needed basis. “Engineers no longer face a forced selection: low-power processor or high-performance processor,” he say. “Rather, the selection for performance or power efficiency can be made instantaneously, as needed, without having to reconfigure.”

All of this plus the rich graphics and user interface FD-SOI enables makes the i.MX 7ULP perfect for “…IoT edge devices, as well as smart home controls, building automation, portable patient monitoring, wearables, and portable scanners.”

This is an excellent read: highly recommended.

Of course, ASN covered the i.mX7ULP when it was first announced (on Samsung’s 28nm FD-SOI) last year – you can still read our coverage here. But it’s good to see the company explaining to their customers how FD-SOI will change the way they build products. BTW, you can get all the i.MX7ULP product details on the NXP website here. NXP has also put together a nifty video on the i.MX7ULP – see it here.

Shanghai & Grenoble tech dev powerhouses team up on SOI for IoT in China and global innovation ecosystem

LetiLogo MinatecLogo SITRI-LOGO-EN-2Three of the world’s More-than-Moore and SOI technology development powerhouses have signed a comprehensive agreement for ongoing collaboration and cooperation in developing new technologies for the emerging IoT market. SITRI of Shanghai, and CEA-Leti and Minatec of Grenoble will work together to accelerate the adoption of their latest technologies and create a global innovation ecosystem for emerging IoT applications (read the press release here).

The framework agreement broadly covers all joint areas of research at SITRI and Leti, including MEMS and sensors, 5G RF front ends, ultra-low power computing and communication, RF-SOI and FD-SOI.

In fact, the trio cites SOI as a key technology in the development of both Moore’s Law and “More than Moore” solutions for the IC industry, as it brings cost, performance, power and integration advantages to the areas of ICs, RF, MEMS, and communications.

“We are confident that this collaboration will be positive for China’s electronics industry, as well as for the Grenoble region’s growing SOI technology ecosystem,” said MINATEC Director Jean-Charles Guibert.

Adds Marie-Noëlle Semeria, CEO of Leti, “Through this partnership, SITRI, MINATEC, CEA-Leti and the entire ecosystem will be able to promote and extend this ecosystem to SOI partners worldwide, and provide SOI solutions to the emerging Chinese IoT market.”

“MINATEC is a world-class international innovation center that fosters a wide range of leading-edge IoT technology research and development which is home to CEA-Leti, the renowned international research institute in microelectronics,” said Charles Yang, President of SITRI. “Through this agreement and SITRI’s established platform for ‘More than Moore’ commercialization, we can accelerate the adoption of these latest technologies and create a global innovation ecosystem for emerging IoT applications.”

GlobalFoundries and Synopsys Streamline the Move to 22nm FD-SOI

By: Tamer Ragheb, Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys

It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT).

GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 1_Benefits of 22FDX body-biasing

Figure 1: Benefits of 22FDX body-biasing

The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 2_22FDX Body Bias Optimizes Performance and Power

Figure 2: 22FDX Body Bias Optimizes Performance and Power

In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include:

  • Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance
  • Low variability and body-biasing capability that can achieve 0.4 volt operation
  • Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent

Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs.

There are four application optimized extensions available with 22FDX (Fig. 3). These are:

  • 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation.
  • 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage.
  • 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications.
  • 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications.
GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 3_22FDX Platform and Extensions

Figure 3: 22FDX Platform and Extensions

GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications.

GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.

Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include:

  • Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization
  • Formality® formal verification with bias-aware equivalence checking
  • IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology
  • IC Validator In-Design physical verification

The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

S3Sadvprgmpic_lowres

Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

S3S15lineup

The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

FinFET or FD-SOI? Designers have a real choice, say experts

Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.

Is there a place for FinFETs? Of course there is. If it’s a really big digital chip –  no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.

But is that really where most designs are?

Cannery Row at twilight

(Photo credit: Monterey County Convention and Visitors Bureau)

If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.

Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.

EDA experts weigh in at EDPS

Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.

EDPSlogoThe session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.

And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”

EDPS_FF_FDSOI_panel

EDPS 2015 panelists debate FinFET vs. FD-SOI. (Left to right: Marco Brambilla (Synapse Design); Kelvin Low (Samsung); Boris Murmann (Stanford); Jamie Schaeffer (GlobalFoundries). (Image courtesy: Richard Goering and Cadence)

In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:

  • Kelvin Low, Sr. Director Foundry Marketing for Samsung
  • Boris Murmann, Stanford professor and analog/mixed-signal expert
  • Marco Brambilla, Director of Engineering at Synapse Design
  • Jamie Schaeffer, Product Line Manager at GlobalFoundries

The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”

There you have it!

Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.

Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).

Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.

So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.

 

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

SatishBagalkotkar_outside

Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.

ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.

Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?

Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.

ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?

SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.synapse_logo_300_ppi

ASN: At what point in the design process do you typically come in? What sorts of services do you offer?

SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.

ASN: What do you see as the advantages of FD-SOI?

SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.

SynapseDesign_FDSOI_v_bulk

An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.

We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.

ASN: Designers of what kinds of chips should be thinking about FD-SOI?

SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.

ASN: Why do they ultimately choose it? Why do they hesitate?

SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.

ASN: Are there special considerations designers should think about before starting a project in FD-SOI?

SynapseDesign_FDSOI_diffSB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.

ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?

SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.

Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.

ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?

SynapseDesign_FDSOI_summarySB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market

ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?

SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.

ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?

SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.

We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.

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Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.

Interview (Leti): How a new platform helps designers get the most out of FD-SOI for IoT, ULP

CEA-Leti Clean Room (© Pierre Jayet)

CEA-Leti Clean Room (© Pierre Jayet)

A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume. Olivier Thomas, who’s in charge of the program and Ali Erdengiz, who’s Business Development Manager for Leti explain how it works.

 

Advanced Substrate News (ASN): What exactly is Silicon Impulse? What services does it offer?

OThomas2

Olivier THOMAS is the project leader of Silicon Impulse for Leti.

Olivier Thomas (OT): Silicon Impulse provides design services from emulation to test program development and qualification (emulation, advanced building blocks and IPs access, full control design flow, industrial MPW, packaging and board, test and qualification).

So you can consider Silicon Impulse as a silicon enablement and development platform: a unique IC prototype development and production hand-off partner for companies in need of the latest low-power semiconductor technologies and heterogeneous integration solutions (FD-SOI, BEOL NVM, MEMS, 3D…). We work with a strong network of industrial partners and offer a single entry point along product maturation.

Silicon Impulse leverages Leti’s* and List’s** expertise as well as top industrial partners belonging to a global network of experts in analog, RF, digital and memory design, as well as hardware/software-integrated solutions.

CEA-Leti Clean Room (©Pierre Jayet)

 

In a nutshell, Silicon Impulse offers:

  • a pool of expertise from device to system
  • access to world-class, leading-edge technologies
  • regularly scheduled industrial multi-project wafer (MPW) shuttles
  • access to a proven supply chain
  • customized collaboration to fit partner needs

[Editor’s note: Click here to download the Silicon Impulse brochure.]

ASN: Who is it aimed at?

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz (AE): We saw that the increasing cost of leading semiconductor technologies, the level of expertise, tools and resources required to develop innovative products using such advanced processes can make it really challenging for new entrants (product and solution innovators). So CEA Leti created the Silicon Impulse initiative to help innovative companies to get their projects off the ground. We provide an advanced silicon development platform, help them develop their IC and/or subsystem and then hand it off to the production supply chain.

We did this because we see that today’s new markets are driven by a variety of applications and new players – it’s not just the big players scaling for PCs and mobiles anymore. IoT is a great opportunity for the emergence of innovations and ideas from new entrants. We’ve been getting more and more requests from partners looking to integrate the advanced technologies developed in Leti such as BEOL NVM and MEMS. They’re thinking outside of the box, so they are also interested in using 28nm FD-SOI while requesting advanced features and specific performance at low-voltage. Leti has always done technology research. Now with Silicon Impulse we provide a new service in collaboration with other industrial partners to help companies evaluate, design, prototype, and launch their products.

ASN: If FD-SOI design is so easy and so close to what designers have done in bulk, why do they need this sort of service?

Leti and List have a long history of launching innovation, as seen here in the CEA-Leti Showroom (©Pierre Jayet)

 

OT: Indeed, one can easily migrate from bulk to FD-SOI and benefit immediately from its low power/low leakage characteristics. However, we’ve seen that many of the companies that port their circuits to FD-SOI don’t exploit the full potential of the technology. Silicon Impulse leverages Leti’s strong expertise and experience in FD-SOI technology from device to Digital/RF modeling and advanced design solutions and maximizes the gains of the technology. Our competence center provides its industrial partners with quick access to information, know-how and silicon proven advanced design and architecture solutions to efficiently manage performance, power consumption and process variability. Here are some examples: PVT sensors, timing fault tracking, control theory module (i.e. algorithm to figure out the optimum energy point), fast feedback loop on the top of tailored charge pump and other blocks to back bias efficiently.

In addition, Leti’s Silicon Impulse’s expertise is not limited to designing FD-SOI IC’s. Leti brings a wealth of system knowledge and application know-how from device technology through embedded software that ensures full success and differentiation for its partners’ projects.

ASN: Why should designers consider FD-SOI?

OT: The 28nm/22nm technology nodes are seen as a long-lived technology node and a sweet spot for performance, power and cost. FD-SOI is optimized for low-voltage, low-power applications that can nevertheless need high performance.

For digital design, the extended range (+/-2V) of back biasing along with PVT sensors, timing fault tracking, theory control module and fast feedback loops controlling the back bias enable efficient process compensation and energy optimization for a wide range of applications (E. Beigne et al. ISSCC’14).

For SRAM design, the un-doped planar technology offers a large portfolio of SRAM bit-cells (High-density, Low power, High-performance) enabling very good performance over a wide voltage range. The Single P-Well bit-cell architecture combined with a wide back bias range enables both low operating voltage and fast access time. In sleep mode, the back bias can be set to minimize the bit-cell standby leakage current and the data retention voltage (O. Thomas et al. IEDM’14).

For RF design, one key aspect shown in the paper presented at ISSCC 15 is the continuous re-configurability through VT adjustment by the back-gate. The Power Amplifier discussed in the paper can pass from a high-linearity/high-efficiency state to a high power state by continuous linear tuning; something that cannot be done in other technologies. At the same time, the 28 FD-SOI allows designers reach much higher FT/Fmax than bulk. The result is higher available gain in mm Wave (as shown in our example at 60GHz). This approach drastically reduces the PA’s power consumption in 90% of the use cases, thus enabling WiGig for example in mobile applications.

ASN: What are the logistics for getting started?

OT, AE: Silicon Impulse can help innovators with their projects from concept through production hand-off. To get started on a project, we do a business review to determine where and how Silicon Impulse can contribute. We can provide architectural advice and shape the product from a very high level, develop a feasibility study and make recommendations as to how to implement the system. Leti and its partners can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, MEMS, 3D components and any other advanced technology to shape a truly unique and advanced yet manufacturable product. Another layer of contribution of Leti, List would be in providing embedded software to complete the whole product. So Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between.

Construction of an extension to the Minatec campus is now underway, which will be the new home to Leti’s Silicon Impulse® service. (Architect’s rendering of the IC Design Competence Center building, north view shown here, ©Futur A Architectes)

 

ASN: You’re running multi-project wafer (MPW) shuttles – can you tell us more about that?

OT: Leti offers its MPW shuttles to open the doors to a wider set of users and projects (some of whom might not have access to or be ready yet for full service foundries). An MPW shuttle serves two main purposes:

  • Enable innovators to test their ideas, especially mixed-signal, analog or RF or any new IP that would require silicon validation in FD-SOI
  • Provide an affordable platform for startups and other small companies to build their prototypes and run small volumes until they can raise enough funds and/or demonstrate market traction to build their own mask set.

However, we’ll also be making an announcement in the near future with details of schedules for planned MPW shuttles with our industrial partners.

ASN: How long will it take to get to a working design?

AE: This is project dependent, but leveraging Leti’s experience and already proven IPs and methodologies it is likely that our partners will develop a successful design even faster than if they did it on their own regardless of whether they used FD-SOI or bulk. Using FD-SOI for digital design targeting low power without compromising performance will certainly get you there faster than using bulk. In addition, the intrinsic characteristics of FD-SOI and much better control of device variability will accelerate analog and RF design and reduce time to market.

ASN: Will the design then be transferable to a full-service, high-volume fab?

OT: The purpose of Silicon Impulse is to ease IC prototype development and enable/accelerate production ramp-up. Silicon Impulse completes the Leti R&D offering by transferring the technology into a manufacturable product. The production is then handed off to a full service fab and/or supply chain partner. We’ll begin announcing the names of these partners shortly.

For information on contacting Leti’s Silicon Impulse service, click here.

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Olivier THOMAS is the project leader of Silicon Impulse for Leti. He received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti’s advanced memory design activity. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

Ali Erdengiz is Business Development Manager for Leti/List. He has spent 20 years in Silicon Valley and held various engineering, marketing, product and business unit management functions at companies such as ST Micro, National Semiconductor, Fujitsu, Altera, Abound Logic and eSilicon. Ali holds a BSEE from ESME, an MSEE from Université Parix XI and an MBA from San Jose State University.

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Minatec_aerial_lores

Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

*CEA-Leti is a research-and-technology organization with a large and word class expertise from device through system integration. It specializes in nanotechnologies and their applications. NEMS and MEMS are also at the core of its activities. Leti is capable of not only developing semiconductor devices (analog, mixed-signal, RF, digital, MEMS) but also integrating them into subsystems using PCB, MCM, 2.5D and 3D technologies as well as developing embedded and application software to deliver full system level solutions.

 

**A sister organization to CEA-Leti, CEA-List conducts R&D in fields that create value for the economy and society. As such, the primary mission is to give businesses the tools they need to turn their innovative ideas into marketable products.

 

Samsung/ChipEstimate video gives strong plug for FD-SOI

In a new YouTube video, Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI, especially for ultra-low-power, IoT, wearables, networking and automotive apps. The five-minute video was taped by ChipEstimate.TV host Sean O’Kane during the Cadence User Conference (CDNLive, Silicon Valley, March 2015 – click here to see it). While the first half addresses 14nm FinFET, starting at the 2:25 mark, it’s all about FD-SOI.

SamsungCDN

Samsung’s Sr. Director of Foundry Marketing, Kelvin Low, makes a strong case for 28nm FD-SOI in a CDNLive interview with ChipEstimate.TV’s Sean O’Kane.

First Kelvin reminds viewers that 28nm will be a long-lived node thanks to its lower costs and the fact that it doesn’t use double patterning. He says Samsung has acquired a number of customers for FD-SOI, and now has the complete ecosystem to support the process technology, from substrate suppliers through the design chain. The key value, he says, is in the extremely low power operation and the low power supply voltage, which translates into long battery life for IoT and wearables. He also says he’s very excited by the prospects for FD-SOI in the automotive domain, where it is especially valued for its enhanced reliability.