For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)
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ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?
Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.
Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.
Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.
ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?
KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.
Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.
KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.
ASN: Can designers get started today?
KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.
Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.
There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.
ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.
KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.
FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.
There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.
AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.
ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?
KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.
AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.
KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
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This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).
A very successful two-day forum on FD-SOI and RF-SOI in Shanghai (September 2015) featured presentations from CEOs, CTOs and VPs at GF, ST, Leti, ARM, Verisilicon, Synapse Design, SITRI, Skyworks, Freescale, TowerJazz, Soitec, Qorvo and many more. Most of the presentations are now available on the SOI Consortium Website, and the rest are expected shortly, so keep checking back.
To download the “Design for FD-SOI” presentations, see the list here.
To download the “RF-SOI Workshop – Interconnected World” presentations, see the list here. (Presentations from all of the major SOI wafer suppliers are also available on this page.)
With much fanfare, GlobalFoundries has officially announced its 22nm FD-SOI offering. Dubbed “22FDX™”, GF says the platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar, targeting mainstream mobile, IoT, RF connectivity and networking markets.
Asked by EETimes why FD-SOI here and now, GF’s CEO Sanjay Jha responded, “The mass market is at 28nm/22nm. Really it is leading-edge pure digital that is the niche.” (Read Peter Clarke’s full piece here.)
And so a new paradigm is born.
With FinFETs relegated to the leading-edge-pure-digital niche, GF says FD-SOI provides the best path for cost-sensitive applications (which is everything else, right?!). Their pitch: 22FDX offers the industry’s lowest operating voltage (0.4 volt), enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. Plus it delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.
It’s been three years since ST announced (in June 2012) that GF would be providing high-volume sourcing for FD-SOI, but you never saw it on GF’s website — til now. As of 13 July 2015, it’s there in a big way. Today, you can finally go to the GF website and see the headline on the homepage, or find out all about the offer on dedicated tech solution pages (click here to check it out yourself).
“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Jha, who was on hand for the big event in Dresden, Germany. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”
And of course it’s good new for the folks at GF’s Fab 1 in Dresden, in the heart of Germany’s “Silicon Saxony” region. GF’s invested another $250 million for technology development and initial 22FDX capacity there (that’s on top of the >$5 billion they’ve invested there since 2009). Further investments to support additional customer demand are planned, plus partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering.
If you read the ASN coverage of the FD-SOI Workshop during LetiDays a few weeks ago, you saw that GF’s 22nm FD-SOI has a 14nm front end and 28nm back end (read it here if you missed it before). At LetiDays, they also talked about body-bias “generators”. In the 22FDX press release they’re referring to it as “…software-control of transistor characteristics to achieve real time tradeoff between static power, dynamic power and performance.”
Here are the offerings in the 22FDX platform, each one targeting a specific area of applications.
22FD-ulp: ulp aka ultra-low power is an alternative to FinFET for the mainstream and low-cost smartphone market. With body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET, says GF. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.
22FD-uhp: uhp aka ultra-high performance – this offers networking applications with analog integration the capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.
22FD-ull: ull aka ultra-low leakage targets wearables and IoT. It delivers the same capabilities of 22FD-ulp, while reducing static leakage to as low as 1pA/μm (pA = picoamp = one million millionth (10-12) of an amp, folks). This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.
22FD-rfa: rfa aka integrated RF and analog. It delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.
GF says they’ve been working closely with key customers and ecosystem partners to enable optimized design methodology and a full suite of foundational and complex IP. Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.
ST: “GLOBALFOUNDRIES’ FDX platform, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum of this technology by expanding the ecosystem and assuring a source of high-volume supply,” said Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”
Freescale: “Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino, vice president of applications processors and advanced technology adoption for Freescale’s MCU group. “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”
ARM: “The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the IP ecosystem needed for customers to benefit from the unique value of 22FDX technology.”
Verisilicon: “VeriSilicon has experience designing IoT SoCs in FD-SOI technology and we have demonstrated the benefits of FD-SOI in addressing ultra-low power and low energy applications,” said Wayne Dai, president and CEO of VeriSilicon Holdings Co. Ltd. “We look forward to collaborating with GLOBALFOUNDRIES on their 22FDX offering to deliver power, performance and cost optimized designs for smart phones, smart homes, and smart cars especially for the China market.”
Imagination: “Next-generation connected devices, in markets from wearables and IoT to mobile and consumer, require semiconductor solutions that provide an optimal balance of performance, power and cost,” said Tony King-Smith, EVP Marketing, Imagination Technologies. “The combination of GLOBALFOUNDRIES’ new 22FDX technology with Imagination’s broad portfolio of advanced IP – including PowerVR multimedia, MIPS CPUs and Ensigma communications – will enable more innovation by our mutual customers as they bring differentiated new products to the market.”
IBS: “FD-SOI technology can provide a multi-node, low-cost roadmap for wearable, consumer, multimedia, automotive, and other applications,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ 22FDX offering brings together the best in low-power FD-SOI technology in a low-cost platform that is expected to experience very strong demand.”
Leti: “FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie-Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES’ 22FDX for connected technologies.”
Soitec: “GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology.”
Choice is a beautiful thing, don’t you agree?
All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.
The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.
The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.
As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.
The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).
Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.
These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.
The 28nm FD-SOI technology offer:
Advances in Technology Development:
The organizers for this event are:
BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.
Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).