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ByAdministrator

The Ever-Expanding 28nm FD-SOI Ecosystem (Samsung Interview, Part 3 of 3)

(New)Kelvin Low Portrait 2015

Kelvin Low, senior director of marketing for Samsung Foundry

Axel_Fischer_Samsung_28FDSOI_sm

Axel Fischer, director of Samsung System LSI business in Europe

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)

~ ~ ~

ASN: Let’s talk a little more about IP availability.

Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.

Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.Samsung_28FDSOI_IP_reuse_14

ASN: In terms of the ecosystem, what remains to be done?

KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.

AF: Especially as you have good support for RF/analog functionality. So, this ecosystem becomes quite important.Samsung_28FDSOI_enablement_11

KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.

As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.

ASN: Any closing thoughts?

KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.

Samsung_28FDSOI_future_15~ ~ ~

This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).

ByAdministrator

When to Choose 28nm FD-SOI and Why (Samsung Interview Part 2 of 3)

(New)Kelvin Low Portrait 2015

Kelvin Low, senior director of marketing for Samsung Foundry

Axel_Fischer_Samsung_28FDSOI_sm

Axel Fischer, director of Samsung System LSI business in Europe

For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)

~ ~ ~

ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?

Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.

Samsung_28FDSOI_lowpower_knobs_13Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.

Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.

ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?

KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.

Samsung_28FDSOI_Vdd_9Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.

KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.Samsung_28FDSOI_PPA_7

ASN: Can designers get started today?

KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.

Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.

There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.

ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.

KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.

Samsung_28FDSOI_bodybias_8FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.

There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.

AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.

ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?

KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.

Samsung_28FDSOI_apps_6AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.

KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.

~ ~ ~

*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).

~  ~ ~

This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).

ByGianni PRATA

Shanghai FD-SOI and RF-SOI Presentations From Top CEO/CTO/VPs on SOI Consortium Website

A very successful two-day forum on FD-SOI and RF-SOI in Shanghai (September 2015) featured presentations from CEOs, CTOs and VPs at GF, ST, Leti, ARM, Verisilicon, Synapse Design, SITRI, Skyworks, Freescale, TowerJazz, Soitec, Qorvo and many more. Most of the presentations are now available on the SOI Consortium Website, and the rest are expected shortly, so keep checking back.

To download the “Design for FD-SOI” presentations, see the list here.

To download the “RF-SOI Workshop – Interconnected World” presentations, see the list here. (Presentations from all of the major SOI wafer suppliers are also available on this page.)

ByAdministrator

It’s Official! GlobalFoundries Launches 22FDX: 22nm FD-SOI in 4 flavors

With much fanfare, GlobalFoundries has officially announced its 22nm FD-SOI offering. Dubbed “22FDX™”, GF says the platform delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar, targeting mainstream mobile, IoT, RF connectivity and networking markets.

Asked by EETimes why FD-SOI here and now, GF’s CEO Sanjay Jha responded, “The mass market is at 28nm/22nm. Really it is leading-edge pure digital that is the niche.” (Read Peter Clarke’s full piece here.)

And so a new paradigm is born.

With FinFETs relegated to the leading-edge-pure-digital niche, GF says FD-SOI provides the best path for cost-sensitive applications (which is everything else, right?!). Their pitch: 22FDX offers the industry’s lowest operating voltage (0.4 volt), enabling ultra-low dynamic power consumption, less thermal impact, and smaller end-product form-factors. Plus it delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

It’s been three years since ST announced (in June 2012) that GF would be providing high-volume sourcing for FD-SOI, but you never saw it on GF’s website — til now. As of 13 July 2015, it’s there in a big way. Today, you can finally go to the GF website and see the headline on the homepage, or find out all about the offer on dedicated tech solution pages (click here to check it out yourself).

GF_FDSOI_website

A snapshot of the GlobalFoundries website page for the new 22nm FD-SOI platform.

GF_FDSOI_apps

Target apps for 22FDX (Courtesy: GlobalFoundries)

“The 22FDX platform enables our customers to deliver differentiated products with the best balance of power, performance and cost,” said Jha, who was on hand for the big event in Dresden, Germany. “In an industry first, 22FDX provides real-time system software control of transistor characteristics: the system designer can dynamically balance power, performance, and leakage. Additionally, for RF and analog integration, the platform delivers best scaling combined with highest energy efficiency.”

And of course it’s good new for the folks at GF’s Fab 1 in Dresden, in the heart of Germany’s “Silicon Saxony” region. GF’s invested another $250 million for technology development and initial 22FDX capacity there (that’s on top of the >$5 billion they’ve invested there since 2009). Further investments to support additional customer demand are planned, plus partnering with R&D and industry leaders to grow a robust ecosystem and to enable faster time-to-market as well as a comprehensive roadmap for its 22FDX offering.

If you read the ASN coverage of the FD-SOI Workshop during LetiDays a few weeks ago, you saw that GF’s 22nm FD-SOI has a 14nm front end and 28nm back end (read it here if you missed it before). At LetiDays, they also talked about body-bias “generators”. In the 22FDX press release they’re referring to it as “…software-control of transistor characteristics to achieve real time tradeoff between static power, dynamic power and performance.”

GF_FDSOI_FBBgraphic

GF slide from 22FDX launch shows the power of forward body-bias (Courtesy: GlobalFoundries)

4 Flavors

Here are the offerings in the 22FDX platform, each one targeting a specific area of applications.

22FD-ulp: ulp aka ultra-low power is an alternative to FinFET for the mainstream and low-cost smartphone market. With body-biasing, 22FD-ulp delivers greater than 70 percent power reduction compared to 0.9 volt 28nm HKMG, as well as performance equivalent to FinFET, says GF. For certain IoT and consumer applications, the platform can operate at 0.4 volt, delivering up to 90 percent power reduction compared to 28nm HKMG.

22FD-uhp: uhp aka ultra-high performance – this offers networking applications with analog integration the capabilities of FinFET while minimizing energy consumption. 22FD-uhp customizations include forward body-bias, application optimized metal stacks, and support for 0.95 volt overdrive.

22FD-ull: ull aka ultra-low leakage targets wearables and IoT. It delivers the same capabilities of 22FD-ulp, while reducing static leakage to as low as 1pA/μm (pA = picoamp = one million millionth (10-12) of an amp, folks). This combination of low active power, ultra-low leakage, and flexible body-biasing can enable a new class of battery-operated wearable devices with an order of magnitude power reduction.

GF_FDSOI_platform

Slide shown during the 22FDX launch summarizes GF’s four FD-SOI flavors. (Courtesy: GlobalFoundries)

22FD-rfa: rfa aka integrated RF and analog. It delivers 50 percent lower power at reduced system cost to meet the stringent requirements of high-volume RF applications such as LTE-A cellular transceivers, high order MIMO WiFi combo chips, and millimeter wave radar. The RF active device back-gate feature can reduce or eliminate complex compensation circuits in the primary RF signal path, allowing RF designers to extract more of the intrinsic device Ft performance.

GF says they’ve been working closely with key customers and ecosystem partners to enable optimized design methodology and a full suite of foundational and complex IP. Design starter kits and early versions of process design kits (PDKs) are available now with risk production starting in the second half of 2016.

What Customers and Partners are saying

ST: “GLOBALFOUNDRIES’ FDX platform, using an advanced FD-SOI transistor architecture developed through our long-standing research partnership, confirms and strengthens the momentum of this technology by expanding the ecosystem and assuring a source of high-volume supply,” said Jean-Marc Chery, chief operating officer of STMicroelectronics. “FD-SOI is an ideal process technology to meet the unique always-on, low-power requirements of IoT and other power-sensitive devices worldwide.”

Freescale: “Freescale’s® next-generation i.MX series of applications processors is leveraging the benefits of FD-SOI to achieve industry leading ultra-low power performance-on-demand solutions for automotive, industrial and consumer applications,” said Ron Martino, vice president of applications processors and advanced technology adoption for Freescale’s MCU group. “GLOBALFOUNDRIES’ 22FDX platform is a great addition to the industry which provides a high volume manufacturing extension of FD-SOI beyond 28nm by continuing to scale down for cost and extend capability for power-performance optimization.”

ARM: “The connected world of mobile and IoT devices depend on SoCs that are optimized for performance, power and cost,” said Will Abbey, general manager, physical design group, ARM. “We are collaborating closely with GLOBALFOUNDRIES to deliver the IP ecosystem needed for customers to benefit from the unique value of 22FDX technology.”

Verisilicon: “VeriSilicon has experience designing IoT SoCs in FD-SOI technology and we have demonstrated the benefits of FD-SOI in addressing ultra-low power and low energy applications,” said Wayne Dai, president and CEO of VeriSilicon Holdings Co. Ltd. “We look forward to collaborating with GLOBALFOUNDRIES on their 22FDX offering to deliver power, performance and cost optimized designs for smart phones, smart homes, and smart cars especially for the China market.”

Imagination: “Next-generation connected devices, in markets from wearables and IoT to mobile and consumer, require semiconductor solutions that provide an optimal balance of performance, power and cost,” said Tony King-Smith, EVP Marketing, Imagination Technologies. “The combination of GLOBALFOUNDRIES’ new 22FDX technology with Imagination’s broad portfolio of advanced IP – including PowerVR multimedia, MIPS CPUs and Ensigma communications – will enable more innovation by our mutual customers as they bring differentiated new products to the market.”

IBS: “FD-SOI technology can provide a multi-node, low-cost roadmap for wearable, consumer, multimedia, automotive, and other applications,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ 22FDX offering brings together the best in low-power FD-SOI technology in a low-cost platform that is expected to experience very strong demand.”

Leti: “FD-SOI can deliver significant improvements in performance and power savings, while minimizing adjustments to existing design-and-manufacturing methodologies,” said CEA-Leti CEO Marie-Noëlle Semeria. “Together, we can collectively deliver proven, well-understood design-and-manufacturing techniques for the successful production of GLOBALFOUNDRIES’ 22FDX for connected technologies.”

Soitec: “GLOBALFOUNDRIES’ announcement is a key milestone for enabling the next generation of low-power electronics,” said Paul Boudre, CEO of Soitec. “We are pleased to be GLOBALFOUNDRIES’ strategic partner. Our ultra-thin SOI substrate is ready for high-volume manufacturing of 22FDX technology.”

You might also want to check out GF’s 22FDX brochure (click here to download it) and watch their technical webinar: Extending Moore’s Law with FD-SOI Technology.

Choice is a beautiful thing, don’t you agree?

ByAdele Hars

Yes, Cisco Is Doing a 28nm FD-SOI Chip! (Part 2 of 3, SF Workshop: FD-SOI Panel Discussion)

More good news: Cisco is working on a 28nm FD-SOI chip. This additional boost to FD-SOI momentum was revealed during the Panel Discussion at the recent FD-SOI/RF-SOI Workshop in San Francisco. The EETimes coverage (which also revealed that Freescale’s putting its next-gen iMX7 microprocessor on 28nm FD-SOI – you can read it here) was quickly shared hundreds of times on LinkedIn.

SemiWiki’s Dan Nenni moderated the panel, which addressed Advantages and Opportunities when Designing with FD-SOI. Panelists included Marco Brambilla, Director of Engineering, Synapse Design; Wayne Dai, Chairman, President & CEO, VeriSilicon; Kelvin Low, Sr. Director, Foundry Marketing, Samsung SSI; Philippe Magarshack, CTO, STMicroelectronics; and Guntram Wolski, Principal Engineer at Cisco Systems.

In case you missed it, we covered the morning’s FD-SOI presentations in a previous post – click here to see it. As we mentioned there, the workshop was a huge success, with over 150 people from over 80 companies in the audience. In the next ASN post we’ll cover the RF-SOI presentations.

 

SF_FDSOI_panel

FD-SOI Panel Discussion during the 2015 San Francisco Workshop (left to right: Daniel Nenni , Semiwiki; Guntram Wolski, Cisco Systems; Philippe Magarshack, ST; Kelvin Low, Samsung SSI; Marco Brambilla, Synapse Design; Wayne Dai, VeriSilicon)

There was lots of anticipation going into the panel discussion, and it turned out to be one of the best parts of what was already a very successful day. There were lots of questions raised, and people commented afterwards that they appreciated that answers were candid and straightforward, while clearly being extremely supportive of FD-SOI.

Kelvin Low, Samsung

Kelvin was asked about the positioning of FD-SOI vs. FinFET at Samsung. He explained that there is no conflict, as each addresses a different set of needs. But 28FD: that’s a sweet spot, he reiterated.

He added that we need more FD-SOI seminars and workshops for the design community, to make people feel comfortable. (And those are in the works!) 

Guntram Wolski, Cisco

It was during this panel discussion that Guntram confirmed that Cisco is working on an FD-SOI based chip. Asked about what he sees as the value of FD-SOI technology, he responded:

  • at 28nm, you see a quarter of the leakage vs. bulk
  • it allows a simpler, fanless cooling system and flexibility in the form factor
  • power is so low with FD-SOI that they ended up being able to eliminate some other programs and pull them onto this ASIC
  • forward body bias enables multiple voltages

Asked why Cisco seems to be alone in adopting FD-SOI, he parried: because CIsco is a leader not a follower! He also confirmed that they’re working with all the foundry partners.

Wayne Dai, Verisilicon

Wayne said he sees IOT/wearables as big opportunity for FD-SOI, since they’re power sensitive apps. He commends ST for opening its IP and breaking the chicken-egg issue. He added that with multi-project wafer (MPW) runs from both Samsung and ST, there will be a lot of work on FD-SOI that will further demonstrate the value. Designing in FD-SOI is no different than bulk, he reminded the audience, adding that he’s expecting FD-SOI will be a three-node solution.

More questions, more answers

When someone asked if FD-SOI is so good, why is nobody manufacturing FD-SOI chips, Kelvin pointed out that there are three foundries in place. They have a solution for double patterning, the ecosystem is now in place, and Samsung will have a fully qualified foundry ready for risk production in March, so stay tuned !

Wayne added that 14FD can be better in many cases than FinFET, and Philippe reminded the audience that Sony is designing with FD-SOI. We’ve passed the critical point.

Asked about the value of FD-SOI in analog design, Philippe noted that quick switching of Vt with FD-SOI is 10x more efficient than bulk . When asked about 14nm cost, he responded that there are savings in limiting or removing double patterning in the backend and the middle of the line. Even with some remaining double patterning, there are 3-4 fewer than FinFET, and 10 fewer mask levels than FinFET.

When someone asked about timing and if it’s too late for 28FD with the leading edge already designing in 14nm FinFET, Kelvin responded that FinFET is sexy, but you need to look at the practical side and value of low power. Guntram said he saw many high volume and low power opportunities at 28nm.

Dan Nenni concluded with the reminder that on SemiWiki, for the last four years the #1 search term has been and continues to be “low power”.

The clear take-away message from the panel was that the FD-SOI solution is real!

In the next ASN post, we’ll review the SF workshop presentations on RF-SOI. (If you’re not already signed up for ASN’s email notifications of new posts, you can do it here.)

 

ByAdministrator

Big Boost for FD-SOI Momentum Seen at SF Workshop – Part 1 of 3: The FD-SOI Presentations (ST, Samsung, EDA & Design Houses)

The FD-SOI/RF-SOI Workshop in San Francisco last week was a huge success. Over 150 people from over 80 companies attended the all-day event. There were excellent presentations, animated Q&A sessions, and lots of networking going on over coffee, lunch and cocktails.  It generated excellent press (click here to see the EETimes feature) and lots of activity on LinkedIn and Twitter.

Everyone agreed it was an outstanding day, with all the presenters emphasizing the value, availability and ramp of FD-SOI. Feedback from the presenters indicates that the workshop spurred a significant boost in interest and opportunities.  As one participant noted, “This was very credible.”

If you didn’t make it to SF, we’ll cover the highlights in three ASN posts over the next few days (yes, it was that good!). Here in Part 1, we’ll cover the FD-SOI presentations. In Part 2, we’ll listen in on what was said during the panel discussion on FD-SOI. And in Part 3, we’ll take a look at the RF-SOI presentations. The actual presentations will all be posted shortly on the SOI Consortium website – keep checking back. But for now, here are some snapshots.

ST

ST’s CTO Philippe Magarshack presented on FD-SOI Advantages for Applications and Ecosystem. He was very clear on the value proposition of FD-SOI, with multiple examples (and a tip of the hat to Soitec, which enabled ST with industrial FD-SOI substrate).

ST’s now got 18 active FD-SOI projects underway, he said. What’s driving it?  FD-SOI is all about integration, he pointed out: digital, analog/mixed-signal and RF for starters. Beyond mobile, he cited three key application segments:

  • networking infrastructure apps – thanks to low SER (soft error rates)
  • IoT – especially for ultra-low voltage
  • automotive – with a good summary of the value (see slide) and an example from video analytics (see slide).

ST_FDSOI_automotive

 

ST_FDSOI_video

He also provided a summary of the key design advantages:

  • effective DVFS
  • FBB (forward body bias) for dynamic transistor Vt (threshold voltage) control
  • simple analog integration (a distinct advantage over bulk and FinFET)
  • best SER (soft error rate)

ST_FDSOIadv

With foundry partner Samsung and a complete design platform, the ecosystem is now in place, he concluded.

Samsung

Kelvin Low, Sr. Director Foundry Marketing, Samsung SSI had a very clear message on the FD-SOI foundry offer: they are in business!

In his presentation, 28nm FD-SOI: Cost Effective Low Power Solution for Long Lived 28nm, he covered the technology migration history: scaling, material then structure innovation.

Driving home the message that 28nm will be a long-lived node, he said the PDK’s ready, foundry services are ready and they’re taking orders. (In fact, there was a whole team from Samsung there, answering additional questions and following up with prospective customers during the breaks.)

Kelvin showed manufacturability and reliability data, and PPA (power, performance, area) benchmarks (see slide).

Samsung28FDSOIppa

For wearable apps, of course, low power is a must. Here, body biasing and low Vdd (supply voltage) are key, and again, 28nm FD-SOI shines (see slide).

Samsung28FDSOIvdd

EDA & IP

Next came excellent presentations by the EDA giants.

Mike McAweeney, Sr. Director IP Product Sales presented Synopsys FD-SOI IP Solutions.

Amir Bar-Niv, Senior Group Director, Product Management, Design IP at Cadence presented FD-SOI: Ecosystem and IP Design.

These were largely the same presentations given by these companies at the Tokyo FD-SOI workshop in December. Click here for ASN coverage of that event and details on those presentations.

Design Experience

Ben-Hamida, High Speed Analog Design Manager, Ciena presented the company’s view of the value of FD-SOI in their new 100Gb/s transceiver (see slide). He was very enthusiastic in his support of FD-SOI, and its ability to deliver on its promises.

Ciena_FDSOI

And finally, Shirley Jin, Sr. Director of Engineering at design house Verisilicon presented very compelling benchmarking data on an ARM Cortex A-7 in her presentation, 28nm FD-SOI Design/IP Infrastructure (see slide). Shirley gave a similar presentation in Tokyo in December. Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. Her presentation presented extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_FDSOI_ARMbenchmark2

 

Members of the SOI Consortium have been organizing these workshops around the world for the last six years (all the presentations from all the workshops are available here) and each one builds the momentum. But the workshops over the last six months (in Shanghai, Tokyo and now San Francisco) have taken that momentum to new levels. So keep an eye out for upcoming events, where more and more users will be sharing their FD-SOI and RF-SOI design experiences.

And stay tuned for Part 2 of ASN’s SF Workshop coverage – where we’ll cover the panel discussion, and the big news that Cisco’s on board with an FD-SOI chip of their own. Part 3 will cover the RF-SOI presentations, and the massive rate of innovation seen there.

ByAdministrator

Tokyo FD-SOI/RF-SOI Workshop (part 2): Sony 1mW FD-SOI GPS steals the show, but great presentations from EDA & design houses, too

The Sony presentation on a 28nm FD-SOI GPS chip for an IoT app, which cut power by 10x (down to 1mW), has gained enormous traction worldwide.  However, that was just one of a dozen excellent presentations made by industry leaders at the recent FD-SOI/RF-SOI workshop in Tokyo.

In part 1 of ASN’s coverage of the workshop (click here if you missed it), we took a quick look at the presentations by Samsung, ST, IBS, IBM and Lapis. Here in part 2, we’ll look at Sony’s, as well as the presentations from the big EDA vendors and the IP and design houses.

All of the presentations are now freely available on the SOI Consortium website (click here for the complete listing).

Low Power SOC design with RF circuit by the FD-SOI 28nm by Kenichi Nakano, Senior Manager, Section8 System Analog Product Department, Analog LSI Business Division, Device Solution Business Group, Sony Corporation

This presentation details Sony’s work on an 28nm FD-SOI version of its CXD5600GF Global Navigation Satellite System receiver LSI for smartphones and mobile products. When the bulk version was first released in 2013, the 10mW power consumption made it the industry’s lowest.  Now, with the 28nm FD-SOI version, they’ve gotten that down to a staggering 1mW – suitable for wearables. The presentation leads off by answering the question: Why FD-SOI? Sony engineers set themselves the challenge of a 0.6V target supply voltage for all logic, SRAM and analog (down from 1.1V in the previous generation). FD-SOI, especially leveraging body biasing, would enable them to attain this goal, providing a wide range of options for optimizing speed, power and area. The various steps and TEGs  (test element groups) are detailed in this presentation, and compared with 28nm and 40nm bulk. The advantages for low-power RF were particularly compelling.  This presentation has generated enormous attention in the press and in social media. For example, a week after EETimes published Sony Joins FD-SOI Club, it had been shared almost 200 times on LinkedIn.

Sony_Tokyo_FDSOI_GPS

(Courtesy: Sony)

 

Creation of high performance IP for FD-SOI by Kevin Yee, Director of Marketing, Cadence

As noted in this presentation, Cadence has existing solutions for 28nm FD-SOI, 14nm FD-SOI and 14nm FinFET-SOI. They have provided full design enablement for ST and Samsung processes. This presentation shows several examples of IP.

Cadence_Tokyo_FDSOI

(Courtesy: Cadence)

 

28nm FD-SOI Design/IP Infrastructure by Shirley Jin, Sr. Director of Engineering, VeriSilicon

Headquartered in Shanghai, Verisilicon provides Silicon as a Platform Services (SiPaaS), taping out 50 chips a year for leading customers at foundries worldwide. This presentation presents extensive, detailed 28nm FD-SOI benchmarking data for the ARM Cortex A7. VeriSilicon has an extensive IP portfolio in 28nm FD-SOI, working design flow and infrastructure to execute the designs.

Verisilicon_Tokyo_28FDSOI_ARMbenchmark

Designing with FD-SOI – Benefits and Challenges by Huzefa Cutlerywala, Sr. Dir. Technical Solutions, Open-Silicon

Open-Silicon is a leader in traditional ASIC solutions, derivative and platform SoCs, hardware and software design and production handoffs. They are a channel partner for ST’s FD-SOI in Japan, have pipe-clean design flows for FD-SOI, and are currently taping out an FD-SOI test chip for a customer. They see FD-SOI as ideal for consumer and networking/telecom/storage/compute applications. This presention lists what they see as the benefits (which are impressive) and challenges (which are fairly minor), and provides some details on GPU and DSP cores.

OpenSilicon_Tokyo_FDSOI_DSPcore

(Courtesy: Open-Silicon)

 

Ultra Low Power Memory Solutions for FD-SOI by Paul Wells, CEO, SureCore

SureCore develops ultra-low power embedded SRAM IP. Making the point that memory typically dominates SoC area and can consume 70% of the power, SureCore sees FD-SOI as an elegant solution. Working samples of their SRAM solution in ST’s 28nm FD-SOI were received in March 2014, showing a 50% dynamic power savings, and high performance at low operating voltage. Extensive comparisons are given in this presentation.

Surecore_Tokyo_FDSOI_SRAM

(Courtesy: SureCore)

 

Synopsys FD-SOI IP Solutions by Mike McAweeney, Sr. Director, IP Product Sales, Synopsys

This presentation gives quite a detailed rundown of the ST-Synopsys 28FD-SOI IP program. Synopsys licenses a comprehensive, silicon-validated 28nm FD-SOI IP portfolio to Samsung’s foundry customers and other manufacturing partners. FD-SOI customers contract with Synopsys for standard Synopsys IP titles, with Synopsys customer support, part numbers, documentation and standard views. Slides 7 and 8 detail the commonly used interface, analog and display IPs available through Synopsys.

(Courtesy: Synopsys)

(Courtesy: Synopsys)

 

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The next FD-SOI/RF-SOI full-day workshop will be held in San Francisco at the Palace Hotel on Friday February 27th 2015, the same week as ISSCC. A broad range of technology and design leaders from across the industry such as Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions in FD-SOI and RF-SOI technologies, including competitive comparisons and product results. Registration is mandatory, free and open to everyone – click here to go to the registration page on the SOI Consortium website. (Lunch will be offered to all the attendees.)

 

By

Successful RF-SOI 2014 International Symposium Held in Shanghai

A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.

The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. ,  a spin-off company from SIMIT,  and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

 

Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)

 

(Courtesy: IBS)

(Courtesy: IBS)

This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.

Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006.  He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)

Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)

Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.

 

The room was full at the Shanghai RF-SOI Workshop 2014

The room was full at the Shanghai RF-SOI Workshop 2014

 

Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.

Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates.  They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate.  (Click here to view the UCL presentation, and here to view the Soitec presentation.)

James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices.  (Click here to view the presentation.)

Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)

RFSOI_Shanghai14_RoundtableDiscussion

Roundtable Discussion at the 2014 International RF-SOI Workshop in Shanghai

The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates.  Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.

 ~ ~ ~

Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original hereMany thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.

ByGianni PRATA

Shanghai RF-SOI and FD-SOI presentations being posted on SOI Consortium website

All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.

The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.

The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.

As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.

 

ByAdministrator

Fully-Depleted SOI Workshop Follows VLSI in Kyoto

The SOI Consortium’s FD-SOI Workshop is returning to Japan. This time it follows on the heels of the big 2013 Symposia on VLSI Technology and Circuits in Kyoto.

The VLSI Symposia run from June 10-14; the SOI Consortium’s workshop on fully-depleted SOI technologies follows on Saturday, June 15, at the Kyoto Research Park. The Consortium event will run from 3 p.m. to 5:30 p.m., just after the Japan Society for the Promotion of Science (JSPS) Symposium on low-voltage devices and circuits (which is being held during the same week as the VLSI Symposia).

Registration for the FD-SOI Workshop is free and open to everyone — click here to access the registration website.

kyoto_2013

These are always lively, well-attended events. Here’s what the Consortium has lined up for the Kyoto workshop.

The 28nm FD-SOI technology offer:

  • 28nm FD-SOI Industrial Solution: Overview of Silicon-Proven Key Benefits – Laurent Le Pailleur, Technology Line Management Director, STMicroelectronics
  • SoC Differentiation using FD-SOI – A Manufacturing Partner’s Perspective – Shigeru Shimauchi, Japan General Manager, GlobalFoundries
  • Ultra Thin Body and Buried Oxide Substrate Supply Chain – Nobuhiko Noto, Deputy General Manager – Advanced Wafers Dept. – Technology & Development, SEH

Design methodologies:

  • Architectural Choices and Design Implementation Methodologies for Exploiting Extended FD-SOI DVFS and Body Bias Capabilities (short course) – David Jacquet, Sr. Principal Engineer, Design & Architecture for Energy Efficiency CPU & GPU Subsystem, STMicroelectronics
  • SoC Design for FD-SOI – Dr. Wayne Dai, CEO, VeriSilicon

Advances in Technology Development:

  • Advances and Silicon Results on 14nm planar FD-SOI Technology – Carlo Reita, CMOS Components Program Manager, CEA-Leti
  • Elements for the Next Generation FinFET CMOS Technology – Terence Hook, Sr. Technical Staff Member, IBM Semiconductor R&D Center (he also wrote an extremely popular ASN article on FinFETs on SOI recently – click here if you missed it)

The organizers for this event are:

  • Horacio Mendez
Executive Director, SOI Industry Consortium
  • Philippe Magarshack
Executive VP, Design Enablement and Services, Digital Sector, STMicroelectronics
  • Joel Hartmann
Executive VP, FE Manufacturing and Process R&D, Digital Sector, STMicroelectronics
  • Mike Noonen
Executive VP, Global Sales, Marketing, Design & Quality, GlobalFoundries

BTW, the presentations from the last SOI Consortium Workshop (April ’13 in Taiwan) are now available on the Consortium website. They’re all really excellent – for example: SoC Differentiation using FDSOI – A Manufacturing Partner’s Perspective, by Subramani Kengeri of GlobalFoundries is packed with side-by-side bulk vs. FD-SOI data.

Next up at ASN, we’ll flag the big SOI-based papers to watch for at VLSI (and there are some knock-your-socks-off results!).