X-FAB is running a series of webinars on very high-temperature design the 18th and 19th of March 2015. A pure-play analog/mixed-signal and specialty foundry, X-FAB’s broad portfolio includes SOI CMOS processes for use at high temperatures up to 225°C. The event is free, but space is limited, so sign up here.
As noted in the program announcement, an increasing number of applications such as automotive engine management require electronic systems that operate reliably at temperatures above 150°C. Designers are facing the challenges of dealing with changes in electrical characteristics, higher leakage current and thermally accelerated degradation. (To read more about high-temp apps on SOI, click here.)
This webinar looks at the device physics, electrical properties of MOSFETs and NVMs, and degradation mechanisms at elevated temperatures up to 200°C. It will discuss the behavior of CMOS when it is operated at higher temperatures and how the issues that arise can be mitigated by process architecture and design techniques.
Soitec and Simgui (Shanghai, China) are partnering on SOI wafer production for RF and power applications. The newly signed deal (read press release here) includes a licensing and technology transfer agreement. Simgui will establish a high-volume SOI manufacturing line using Soitec’s proprietary Smart Cut™ technology to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide. Beyond this initial cooperation, the two companies plan to expand their collaborative efforts in the future to take advantage of their synergies.
A team from King Abdullah University of Science and Technology (Saudi Arabia) has published an article in Advanced Materials (22 February 2014) entitled Flexible and Transparent Silicon-on-Polymer Based Sub-20 nm Non-planar 3D FinFET for Brain-Architecture Inspired Computation. As subsequently described in an article in Nanowerk (article here), “…the team demonstrates a pragmatic approach to transforming silicon-on-insulator (SOI) based state-of-the-art FinFET into flexible and semi-transparent silicon-on-polymer FinFET while retaining high performance and integration density.” This marks the industry’s first FinFET layer transfer, team member Dr. Muhammad Mustafa Hussain told ASN.
Reproduced with permission
An industry standard 8′′ SOI wafer based ultra‐thin (1 μm), ultra‐light‐weight, fully flexible and remarkably transparent state‐of‐the‐art non‐planar three dimensional (3D) FinFET is shown. It has sub‐20 nm features and the highest performance ever reported for a flexible transistor. (Courtesy: WILEY-VCH Verlag GmbH, Advanced Materials and King Abdullah University of Science and Technology. Reprinted with permission.)
By Handel Jones
IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry. The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.
We conclude that:
Here is a brief summary of our findings.
High volume applications need lower cost per transistor in order to use the new generation of process technologies. It is, consequently, appropriate to evaluate the options for continuing the pattern of lower cost per gate, with the analysis of different technology options.
After the 28nm node, the decreasing cost-per-gate trend with reduction in feature dimensions for bulk CMOS is reversed: at 20nm, cost-per-gate starts to increase rather than decrease.
Cost Per Gate Reduction Trends
The impact of not reducing cost per gate is one of the most serious challenges that the semiconductor industry has faced within the last 20 to 30 years. It is, consequently, appropriate to evaluate whether other options are available that can allow scaling to 20nm and smaller feature dimensions to be effective in cost and power consumption because of the large financial impact on the semiconductor industry of not continuing with Moore’s Law.
Wafer Cost Analysis
Our analysis considers depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.
Already at 28nm, the wafer cost is lower for FD-SOI than for bulk HKMG CMOS, although with a relatively small difference. The key reason for the lower cost of FD-SOI is the smaller number of mask and processing steps.
The cost analysis is based on eight-layer metal and 3Vt levels. The following graph is built from the more detailed analysis in our report.
Furthermore, while the difference in total yielded wafer cost at 28nm and 20nm is not very large, it is very important to remember that the FD-SOI technology has the added advantage of providing significantly lower leakage and higher performance than the bulk CMOS.
The reality is that performance of 28nm FD-SOI is 15% better than 20nm bulk CMOS and extends the lifetime of the 28nm technology node. Lower cost, lower power consumption, higher performance, the conclusions are clear.
The situation is even more compelling at 14/16nm.
The wafer cost for 14nm FD-SOI is 18.4% lower than 16nm FinFET. A key factor contributing to the high cost of FinFET wafers is that of the extensive inspection steps required to ensure high yield and high reliability. A number of wafer processing steps need to be tightly controlled and monitored with the processing of FinFET structures. The result is that depreciation cost per wafer for FinFET structures is significantly higher than for FD-SOI.
Note: the generation we call 20nm FD-SOI in our report is called “14FD” by ST Microelectronics, as they also position it as a competitor to 14/16nm FinFET.
While wafer cost is an important factor, die cost is a more vital factor for most companies. Our analysis includes yielded wafer cost, gross die/wafer and yield.
At 28nm, FD-SOI has higher yield, slightly lower die cost (3%) and 30% lower power consumption than bulk CMOS. At 20nm, FD-SOI die cost is 13% lower than bulk CMOS, has higher yield, and is expected to provide 40% lower power consumption.
At 14nm/16nm, the FD-SOI die cost for a 100mm2 die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.
The lower cost of the FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI at this technology node.
However, despite the fact that FD-SOI is clearly more cost effective, large investments are being made by the pure-play foundries in 14/16nm FinFET wafer processes, and while FinFETs will be needed in the future, the issue is timing. It is clearly in the interest of the fabless industry to pay lower die prices, and collaboration with the foundry vendors is needed in this arena. The power structure in the industry has moved too much in favor of the provider rather than the user.
For the fabless industry, the key requirement for FD-SOI is to establish supply chains that can support the participation in high-volume end markets. The fabless companies need to be much more active in ensuring that their needs are being satisfied.
Strategic Considerations Within the FD-SOI Supply Chain
Strategic considerations within the FD-SOI supply chain include the following:
An ecosystem needs to be set up for FD-SOI, and it is important for the electronics industry that this ecosystem is established.
There are many advantages for FD-SOI to be widely adopted for high volume, low cost, and lower power applications in the future. It is important for the semiconductor industry to be willing to make investments to provide optimum solutions to its customers rather than follow the roadmap of a specific company. The fabless companies need to be proactive in supporting the supply chain within an FD-SOI ecosystem.
Timing of the migration to 20nm, 14nm, and 10nm technology nodes need to be based on cost, power consumption, and performance metrics that can be easily verified. Being short-term focused and not willing to adopt new concepts can have large cost penalties within the foundry-fabless environment.
FD-SOI technology can be viable in many applications for the next ten years. The semiconductor industry needs to be willing to make the investments for the future rather than responding to short-term pressures.
Cost penalties resulting from very high design costs and long time-to-market can have a serious impact on the competitiveness of semiconductor vendors that select the FinFET approach at 14/16nm. Semiconductor companies that are participating in fast-moving markets cannot tolerate the additional costs of design and long time-to-market associated with trying to fine-tune technologies that are inherently high cost.
While migration to FinFETs may be required beyond the 10nm node, until then FD-SOI represents the best approach for many of the high volume segments of the semiconductor industry.
The reality is that the foundry vendors will not invest unless they have a high probability of getting customers. This means that the customers need to provide the leadership and accept that the present roadmaps in the industry will not provide them with the best financial returns.
Soitec Sr. VP (and FD-SOI wafer guru) Christophe Maleville has written a very good, high-level piece in the Global Semiconductor Alliance (GSA) Forum. Entitled Technology Selection Implications Intensify and Options are Limited, the piece examines cost-per-gate trends and explores roadmap options. He shows how FD-SOI provides a path forward with continued scalability, significant cost advantage and execution risk reduction vs. all other options. (Read the article here – GSA membership not required.)
(Images courtesy: Debiotech)
Debiotech has debuted the JewelPUMP2, a new product dedicated to the Diabetes Type 2 market, based on Debiotech’s innovative JewelPUMP platform (press release here). By using its JewelPUMP platform, which is already in the industrialization phase and in preparation for the CE marking, Debiotech will be able to introduce the JewelPUMP2 shortly after its JewelPUMP for Type 1 patients, while ensuring the same degree of miniaturization, safety and reliability.
Back in 2009, Debiotech wrote in ASN (click here to read the article) about their Nanopump™, a volumetric membrane pump, at the heart of their systems. Co-designed by Debiotech and ST, and manufactured by ST, the pump consists of a membrane micromachined in an SOI wafer, which is in turn sandwiched between two Pyrex™ plates with throughholes. A piezoelectric actuator moves the membrane to compress and decompress the fluid in the pumping chamber.
FD-SOI could be the “tipping point” for SOI, supply chain expert Bill Kohnen indicated in a presentation at the Semiconductor Technical Purchasing Conference last fall. (See his ppt here.) He suggested, “Purchasing and Supply Chain Organizations at Foundries and Device Manufacturers that need SOI wafers need to closely monitor the supply chain as demand resulting from FD-SOI applications may be the tipping point for capacity issues.” He concludes that the industry consortiums will be helpful in avoiding a “bullwhip effect”.
Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. hosted an “SOI Technology Summit” in Shanghai, China.
Executives of leading companies, universities and institutes, covering all the segments (substrate, design, manufacturing, EDA, IP, etc.) gathered to discuss the solutions to scaling challenges and the market opportunities for FD-SOI in China.
Handel Jones from IBS presented the IC market overview (available here) and detailed the cost difference between the different available technologies. He made the point that FD-SOI is cost competitive at 28nm and has the advantage at 20nm.
David Jacquet from ST highlighted (available here) the design benefits of back-biasing (the FD-SOI version of body biasing), which is only going to be available in FD-SOI technology since it cannot be implemented in planar bulk or FinFET in an effective manner. ST showed how back bias can provide real time optimization of the power-performance trade off and therefore give the most efficient mobile power saving results.
XMC’s Simon Yang gave a foundry manufacturing perspective on FD-SOI technology (available here), confirming that FD-SOI has a lot of advantages. In particular, it is perceived as the simplest way to enter the realm of fully depleted technologies. Also, he emphasized the necessity that the cost of FD-SOI be lower than competitive technologies, which aligned well with Handel Jones’ cost analysis. The wafer manufacturers also confirmed that the substrate price will enable the technology to be lowest cost.
Zhongli Liu, a very highly respected professor at IM CAS urged the Chinese IC industry to see the golden opportunity in FD-SOI technology. He detailed the technology benefits with well-chosen case studies (available here) and concluded that FD-SOI has broader markets since it has perfect features to match the needs of the mobile applications.
Rama Divakaruni from IBM presented a compelling talk on the IBM scaling path at 14nm, 10nm and 7nm (available here). For calculation-intensive applications such as servers, IBM is developing a 14nm FinFET on SOI with eDRAM that provide significant value propositions. Rama reminded the audience that IBM has developed both FD-SOI and FinFET on SOI, the latter being more adapted for IBM’s applications. However, depending on application and design style FD-SOI might be better suited.
SEH, SunEdison and Soitec presented wafer specifications and available capacity for RF-SOI, FD-SOI and FinFET on SOI. They showcased RF-SOI to demonstrate that SOI can be a mainstream solution meeting the cost and volume of the market demand.
Panel discussions at the end of the workshop were passionate regarding China’s opportunity to develop FD-SOI capacity, which could be a great accelerating factor for the China IC industry. This would require a commitment from foundries and design companies, which all agreed looks like the right thing to do.
The world’s largest maker of silicon wafers, Shin‐Etsu Handotai (SEH) says it’s meeting the specs for FD-SOI wafers, and can quickly expand capacity to meet rising demand.
SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) Last year, the two companies extended their licensing agreement and expanded their technology cooperation.
The specs for FD-SOI wafers are very exacting. As Soitec has pointed out, required silicon uniformity across a full 300mm-diameter wafer corresponds to about 5mm (less than a quarter of an inch) over the distance between Chicago and San Francisco.
Here’s what SEH is saying:
Presentations from the Kyoto FD-SOI workshop – including an excellent short course on FD-SOI design techniques – are now freely available on the SOI Consortium website.