Tag Archive wafers

SOI for RF & Low Power ICs

When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management.

The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves significantly the high- frequency behavior of the chip: first, because the buried insulating layer reduces part of the electromagnetic field propagation; second, because bonded SOI technology enables the use of a highly resistive (intrinsic silicon) handle wafer, dramatically reducing both resistive losses and crosstalk. Read More

ATDF MuGFET Development Program

In January of this year, Soitec announced its participation as the SOI substrate supplier in an ATDF development program focusing on multi-gate field effect transistor (MuGFET) technology for the 45-nm node and below. Soitec has now presented joint papers with Texas Instruments and Infineon Technologies at various technical conferences on MuGFETs, which are promising non-planar CMOS transistors that improve performance and minimize current leakage •

Soitec Characterization Lab

Now in its third year, Soitec’s Characterization Lab in Bernin proposes a whole battery of electrical and physico-chemical tests such as Psi-Mos, Hg-fet, CV, Box integrity, BMD and SECCO on SOI, sSOI and new materials. R&D researchers in the lab are developing new characterization techniques for future needs. The lab is audited regularly by customers, and is ISO 9001/14001 compliant •

SOI By the Book

A new book, SOI Device Technology by Makoto Yoshimi, PhD, covers the history of SOI, the floating body effect and a variety of LSI applications.

Language: Japanese Publisher: ED Research, Co. (Tokyo, Japan) www.edresearch.co.jp/FocusRepo/soi.html

An SOI pioneer (he began his research over 20 years ago for Toshiba), Makoto Yoshimi is now Chief Scientist of Soitec Asia. “This book describes what SOI is all about”, he says, “and provides an introduction for device engineers and graduate students.”

Dr. Shigeto Maegawa of Renesas Technology Corp. (Japan) notes that the book “…captures the enthusiasm of the engineers who worked so tenaciously to make SOI a reality.” •

WORLD’S FIRST GaN-ON-INSULATOR

Here’s a quick review of some recent Smart Cut activity.

March 2005 – WORLD’S FIRST GALLIUM NITRIDE (GaN)-ON- INSULATOR SUBSTRATE

Soitec announced that its Smart Cut technology was used to split and transfer a thin layer of GaN from a high-quality GaN donor wafer onto a carrier wafer— generating the world’s first single- crystal, thin-film gallium nitride (GaN)-on-insulator substrate. This represents a critical step forward in enabling the development of high-performance blue and white light-emitting diodes (LEDs), as well as for improving current and future device performance in radio-frequency (RF) and discrete power applications Read More

GaN On the Move

• High Growth Projected for GaN

According to a recent report in “SST” magazine, the Silicon Valley-based market research firm Strategies Unlimited is projecting substantial growth for the gallium nitride (GaN) market. Worth $3.2 billion in 2004, the market is expected to increase to $7.2 billion over the next five years, making it one of the most successful compound semiconductor materials. The report, entitled “Gallium Nitride 2005 – Technology Status, Applications, and Market Forecasts”, says that white LEDs account for over half of the GaN-related LED market. It also sees big growth coming Read More

45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI

The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness).

Courtesy of Texas Instruments, Infineon and Advanced Technology Development Facility (ATDF, a subsidiary of SEMATECH)

The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors (planar & non-planar), ESD structures, Kelvin structures and various test circuits (Ring Oscillators, loaded gates, Current Mirrors, OP-AMPs, SRAM cells, and reliability test sites). Read More