Year 2010Tyndall claims first junctionless transistor
[Semiconductor Today]

    Year 2009Presentation: Silicon results of ARM core 1176 in SOI – A 40% power reduction
[by Remy Pottier, Jonathan Tong, Chris Hawkins, Roma Kundu and Jean-Luc Pelloie, ARM]

Junctionless multigate field-effect transistor
This paper describes a metal-oxide-semiconductor (MOS) transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.
Chi-Woo Lee, Aryan Afzalian, Nima Dehdashti Akhavan, Ran Yan, Isabelle Ferain, and Jean-Pierre Colinge
[Applied Physics Letters, Vol. 94, pp. 053511:1-2: 2009]

Electrostatic Discharge Effects in Fully Depleted SOI MOSFETs with Ultra-Thin Gate Oxide and Different Strain-Inducing Techniques
The ESD sensitivity of 65-nm fully depleted SOI MOSFETs (with thin silicon body) used as output buffer devices is studied. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion that allows us to univocally identify the device failure. Finally, we analyze the impact of device geometry and strain engineering on the ESD sensitivity.
Alessio Griffoni, Augusto Tazzoli, Simone Gerardin, Eddy Simoen, Cor Claeys, and Gaudenzio Meneghesso
[30th Electrical Overstress/Electrostatic Discharge Symposium, 2008, pp. 59-66]

Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs
As MuGFETs are promising contenders for the end of the silicon Roadmap, their high-temperature behaviour needs to be addressed. In this work we investigate the variations of the subthreshold slope (SS) of double-gate devices and MuGFETs with intrinsic doping as a function of the temperature and fin width. Focus is placed on the superlinear behaviour of SS occurring above a certain temperature threshold. Numerical simulations are performed using Comsol Multiphysics™ and a 1D analytical model is developed. The model, which includes the effect of film and gate oxide thickness, is shown to accurately fit the numerical data. A new definition for the subthreshold slope under high-temperature operation is proposed. The high-temperature subthreshold slope degradation is shown to increase with fin width.
Jean-Pierre Colinge, Dimitri Lederer, Aryan Afzalian, Ran Yan, Chi-Woo Lee, Nima Dehdashti Akhavan
[Microelectronic Engineering, Vol. 86, Issue 10, pp. 2067-2071, 2009]

Junctionless MuGFETs
This paper describes the simulation of the electrical characteristics of a new transistor concept called “Junctionless MuGFET”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical property than classical inversion-mode devices with S&D PN junctions.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti, J. P. Colinge
[Proceedings EUROSOI Conference, 2009]

Quantization effects in capacitance behaviour of nanoscale Si MuGFETs
An unusual bump in the gate capacitance characteristics of Si nanoscale MuGFETs is presented and explained here through 3D NEGF quantum simulations. As higher order subbands are populated when the gate voltage is increased, the channel moves closer to the surface. This increases the slope in the I_d-V_g and creates the bump in the C_g(V_g) curve as the centroid of the charge moves closer to the Si/SiO₂ interface and the capacitance is increased.
A. Afzalian, C.-W. Lee, R. Yan, N. Dehdashti, I. Ferrain, J.-P. Colinge
[Proceedings EUROSOI Conference, 2009]

    Year 2008Drain Breakdown Voltage in MuGFETs: Influence of Physical Parameters
This paper analyzes the drain breakdown voltage of multigate MOSFETs and the influence of parameters such as doping concentration, fin width, and gate length. The good electrostatic control of the active area by the multigate structure improves the drain breakdown voltage, which increases as the fin width is decreased. Increasing the channel doping concentration improves the drain breakdown voltage as well.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Weize Xiong, Jean-Pierre Colinge
[IEEE Transactions on Electron Devices, Vol. 55, no. 12, pp. 3503-3506, 2008]

Influence of Gate Underlap in AM and IM MuGFETs
The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode (AM) devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode (IM) FETs.
Chi-Woo Lee, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge
[Proceedings of European Solid-State Device Research Conference (ESSDERC), pp. 238-241, 2008]

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth
This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance.
N. Collaert, R. Rooyackers, A. Hikavyy, A. Dixit, F. Leys, P. Verheyen, R. Loo, M. Jurczak, S. Biesemans
[Thin Solid Films, Vol. 517, Issue 1, pp. 101-104 ]

Accumulation-mode and inversion-mode triple-gate MOSFETs
This work analyzes the performance of very narrow triple-gate SOI MOSFETs on the basis of experimental and 3D simulation data. Short channel effects (SCEs) are quite reduced in those devices due to the good electrostatic control by the surrounding gate and the high L_g/W_fin ratio. The experimental data indicate that SCEs of accumulation-mode (AM) triple gate devices are comparable to those observed in inversion-mode (IM) devices down to a gate length of 50 nm. This makes AM triple gate (or more generally, multi-gate) MOSFETs interesting devices for digital applications.
R.Yan, A.Afzalian, C.-W. Lee, N.Dehdashti Akhavan, W.Xiong, J.-P. Colinge
[Proceedings of China-Ireland International Conference on Information and Communication Technologies (CIICT 2008), pp. 627-630, Sept. 2008]

Innovative device architectures for Nanoscale CMOS
Nadine Collaert, IMEC
[4th Sinano-Nanosil Workshop 2008]

Influence of Fin Width on the Intrinsic Voltage Gain of Standard and Strained Triple-Gate nFinFETs
This work studies the influence of the fin width on the intrinsic voltage gain of standard and strained Si (sSOI) n-type triple-gate FinFETs with high-k dielectrics and metal gate. It is demonstrated that independent of the fin width the application of strain improves the device transconductance. On the other hand, the device output conductance shows a high dependence on the fin width in strained FinFETs with respect to standard ones. The output conductance degrades if narrow fins are used and improves for wide fins. Narrow strained FinFETs show a degradation of the Early voltage compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect.
M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert and C. Claeys
[ECS Transactions, Vol. 14, Issue 1, pp. 253-261]

Reliability issues in MuGFET nanodevices
In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare the TDDB behavior of MuGFET and planar devices and we will show that if adequate processing is used, the triple-gate architecture does not alter the behavior of the time-dependent dielectric breakdown for different gate voltages and temperatures. Next we discuss the Bias Temperature Instability (BTI) behavior of MuGFET CMOS devices. Novel interface passivation techniques as well as the impact of different dielectric nitridation techniques on BTI are discussed, showing similar BTI dependence on Nitrogen incorporated in MuGFET dielectrics as in planar devices. Finally we also discuss the ESD performance of MuGFET devices and we demonstrate that reasonable intrinsic ESD performance can be obtained, but achieving this desired ESD-robustness is found to be critically dependent on various design and process parameters. As a result the design of ESD protection for FinFET technology appears to be a challenging task for the future.
G. Groeseneken, F. Crupi, A. Shickova, S. Thijs, D. Linten, B. Kaczer, N. Collaert, M. Jurczak
[IEEE International Reliability Physics Symposium, 2008, pp. 52-60]

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations
In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation of the threshold voltage shift (ΔV_TH) for any arbitrary location of the doping atom in the transistor. Based on an analysis of a sub-20 nm trigate MOSFET device, we find that the typical variation of V_TH per doping atom is a few tens of mV. Inversion-mode (IM) trigate devices are more sensitive to the doping fluctuation effects than accumulation-mode (AM) devices. The threshold voltage shift arising from doping fluctuations is maximum when the doping atom is near the center of the channel region, which means the original SOI film doping, the random contamination effects or any other impurity doping in the channel region is more important than atoms introduced in the channel by the S/D implantation process for sub-20 nm transistors.
Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, Aryan Afzalian, Chi-Woo Lee, Nima Dehdashti, J.P. Colinge
[Solid-State Electronics, Vol. 52, No. 12, pp. 1872-1876, 2008]

MultiGate SOI MOSFETs: Accumulation-Mode vs. Enhancement-Mode
The performances of accumulation-mode and inversion-mode Multigate FETs are compared. Both simulation and experimental data are presented. Accumulation-mode devices have a higher current drive and less process variability than inversion-mode FETs.
A. Afzalian, D. Lederer, C.W. Lee, R. Yan, W. Xiong, C. Rinn Cleavelin, JP Colinge
[IEEE 2008 Silicon Nanoelectronics Workshop, P1-6, June 15-16, Honolulu, USA, 2008]

Conformal Doping of FINFET's: A Fabrication and Metrology Challenge
This article deals with the developments in the measurement and identification of conformality which is a key function in conformal doping. For this purpose this paper extensively uses SSRM to characterize the vertical/lateral junction depths, concentration levels and degree of conformality. As a complement to the SSRM technique this paper developes a concept based on resistance measurements of fin's which allows to map the sidewall doping across the wafers and provides fast feedback on conformality. The concept uses the reduction of the sheet resistance of a fin which was covered with a hardmask during the implantation, as a measure for the degree of side wall doing. The concept is supported by theoretical simulations and verified using tilted implants.
W.Vandervorst, P.Eyben, M.Jurzack, B.Pawlak, R.Duffy
[International Symposium on VLSI Technology, Systems and Applications, 2008, p. 158]

Material Aspects and Challenges for SOI FinFET Integration
M. J. H. van Dal, G. Vellianitis, R. Duffy, B. J. Pawlak, L-S Lai, A. Hikavyy, N. Collaert, M. Jurczak, R. J. P. Lander
[213th ECS Meeting, Abstract 636, © The Electrochemical Society]

From Gate-All-Around to nanowire MOSFETs
The classical MOSFET is reaching its scaling limits and "end-of-roadmap" alternative devices are being investigated. Amongst the different types of SOI devices proposed, one clearly stands out: the multigate field-effect transistor (multigate FET). This device has a general "wire-like" shape. Multigate FETs are commonly referred to as "multi(ple)-gate transistors", "FinFETs", "tri(ple)- gate transistors", "GAA transistors", etc. This paper describes the reasons for evolving from single-gate to multi-gate structures. It also describe some issues in ultra-small devices, such as doping fluctuation effects and quantum confinement effect.
J.P. Colinge
[International Semiconductor Conference, Sinaia, Romania, pp. 11-17, Oct. 2007]

ESD Sensitivity of 65-nm Fully Depleted SOI MOSFETs with Different Strain-Inducing Techniques
The role of this study is to further investigate the ESD sensitivity of new a generation 65-nm Fully Depleted SOI MOSFETs, with particular attention to the strain engineering. The focus is on the devices that need to be protected from ESD, rather than on the protection structures themselves. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion based on sub-threshold drain current that allows us to univocally identify the device failure (i.e. filament between source and drain and/or gate-oxide breakdown). Finally, we show that the failure voltage depends on the strain level and the gate length, indicating that the strain-engineering may have a non-marginal impact on the reliability of advanced CMOS devices. Furthermore, we show the absence of filament in sCESL+SOI MOSFETs.
A. Griffoni, A. Tazzoli, S. Gerardin, G. Meneghesso, E. Simoen and C. Claeys
[International ESD Workshop, 2008]

FinFET technology for analog and RF circuits
FinFET technology presents a competitive alternative to planar CMOS as it features a better control of the short channel effects. This results in improved digital and analog performances. The radio-frequency (RF) behavior is however affected by a large level of parasitics. In this paper, we explain how technological options and device design affect the FinFET performance. In addition, the challenges and opportunities for both wideband modeling and the design of analog and RF circuits are identified and discussed.
B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sanssen, G. Groeseneken, S. Decoutere
[14th IEEE International Conference on Electronics, Circuits and Systems, 2007, pp.182-185]

Quantum-mechanical effects in nanometer scale MuGFETs
Solving the Poisson and Schrödinger equations self-consistently in two dimensions reveals quantum-mechanical effects that influence the electron concentration, the threshold voltage and the subthreshold slope of MuGFETs. The average electron concentration needed to reach the threshold voltage depends on the gate configuration and on the device geometry. The dependence of the energy of the subbands on the different gate configurations is studied, and the relation between threshold voltage and the lowest subband energy is investigated. Due to a dynamic threshold voltage effect, the drain current is lower in the quantum-based drain current model than in classical simulations. This dynamic increase of threshold voltage is due to an increase of the subband energy with the electron concentration. This effect degrades the subthreshold slope. It is observed in non-symmetrical devices (FinFET, tri-gate), but not in symmetrical structures (GAA). This gives symmetrical devices like GAA nanowires an intrinsic advantage compared to the other types of devices.
Se Re Na Yun, Chong Gun Yu, Jong Tae Park, Jean Pierre Colinge
[Microelectronic Engineering Vol. 85, pp. 1717–1722, 2008]

Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors
The minimum energy of the first conduction subband varies with gate voltage in trigate silicon-on-insulator metal-oxide-silicon field-effect transistors (MOSFETs) in subthreshold operation. In an inversion-mode trigate device, the energy level of the lowest subband increases with electron concentration, while it decreases under the same conditions in some accumulation-mode devices. As a result of this quantum effect, the subthreshold swing of accumulation-mode trigate FETs is smaller than predicted by classical theory. This effect is not observed in fin-shaped FETs and gate-all-around MOSFETs and can be amplified by modifying the device cross section. Jean-Pierre Colinge, Aryan Afzalian, Chi-Woo Lee, Ran Yan, and Nima Dehdashti Akhavan
[Applied Physics Letters 92, 133511, 2008]

The New Generation of SOI MOSFETs
[Romanian Journal of Information Science and Technology, Volume 11, Number 1, 2008, pp. 3-15]

Doping Fluctuation Effects in Trigate SOI MOSFETs
Random doping fluctuation effects are studied in n-channel Trigate SOI MOSFETs using numerical simulations. The presence of a single positive doping impurity atom increases the threshold voltage. Electrical parameters vary with the polarity and the physical location of the impurity atom.
Ran Yan, Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, and Jean-Pierre Colinge
[Proceeding 4th EuroSOI Workshop, pp.65-66 , 2008]

Evidence for Substrate Bias Effects in SOI ΩFETs
It is generally accepted that, due to strong coupling of the lateral gates, narrow SOI Multiple-Gate FETs (MuGFETs) are immune to substrate effects [1]-[3]. Nevertheless, in this work we present experimental evidence for significant substrate bias effects in narrow SOI ΩFETs, consisting in the strong variation of the drive current, transconductance and gate-induced drain leakage current (GIDL), with invariant threshold voltage, subthreshold slope and DIBL. The origin and possible implications of the observed effects are discussed.
T. Rudenko, V. Kilchytska, N. Collaert, M. Jurczak, A. Nazarov and D. Flandre
[EUROSOI Workshop Proceedings: 4th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, 2008, pp. 137-138]

Hydrogen as Source of High-Temperature Charge Instability in the Buried Oxide of SOI Structures and MOSFETs
A. Nazarov, V. Lysenko, D. Flandre and J.P. Colinge
[Proceeding 4th EuroSOI Workshop, pp.113-114 , 2008]

Influence of Carrier Confinement on the Subthreshold Swing of Multigate SOI MOSFETs
The minimum energy of the first conduction subband varies with gate voltage in trigate SOI MOSFETs in subthreshold operation. In an inversion-mode device, the energy level of the lowest subband increases when the electron concentration increases, while it decreases under the same conditions in some accumulation-mode devices. As a result of this quantum effect, the subthreshold swing of accumulation-mode trigate FETs is smaller than predicted by classical theory, while that of inversion-mode devices is higher. This effect is not observed in FinFETs and GAA MOSFETs and can be amplified by modifying the device cross section.
Jean-Pierre Colinge, Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee and Ran Yan
[Proceeding 4th EuroSOI Workshop, pp.61-62 , 2008]

Ultra Scaled MultiGate SOI MOSFETs: Accumulation-Mode vs. Inversion-Mode
The performances of accumulation-mode and inversion-mode Multigate FETs in ultra scaled devices are compared through device simulations. We show that for sub 10nm cross dimensions, device performances (subthreshold slope, threshold voltage…) depend mainly on cross section size and bias voltage and very little on channel doping.
Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, Ran Yan and Jean-Pierre Colinge
[Proceeding 4th EuroSOI Workshop, pp.47-48, 2008]

Unusual noise behavior versus temperature in nFinFETs on silicon on insulator (SOI) substrates processed with different strain techniques
The impact of strain techniques on the low frequency (LF) noise in nFinFETs on SOI substrates devices is reported. Five process conditions with different stressor methods are studied. A carrier number fluctuation dominant flicker noise has been observed for all devices studied. An unusual noise spectrum was observed specifically for the devices which received a Selective Epitaxial Growth (SEG) process. A detailed study of noise versus temperature (150K-300K) was performed on these devices.
Guo, W.; Routoure, J.; Cretu, B.; Carin, R.; Simoen, E.; Mercha, A.; Collaert, N.; Put, S. and Claeys, C.
[EUROSOI Workshop Proceedings: 4th Workshop of the Thematic Network on Silicon-on-Insulator Technology, Devices and Circuits, 2008, pp. 141-142]

3D simulation of Nanowire by Full-Real Space NEGF Simulator
In this article, we present the effects of device parameters variations on the electrical characteristics of rectangular Nanowire. Our three dimensional (3D) device simulator is based on the Non Equilibrium Green Function (NEGF) formalism. Starting from a basic structure GAA Nanowire with a gate length of 10 nm, variation of gate length and channel thickness was carried out in connection with the numerical calculation of device characteristics. In this work Quantum transport equations are solved in 3D by NEGF method in active area of the device to obtain the charge density and Poisson’s equation is solved in entire domain of simulation to get potential profile.
Nima Dehdashti, Aryan Afzalian, Chi-Woo Lee, Ran Yan, G. Fagas and Jean-Pierre Colinge
[Tyndall National Institute]

Comparison of different surface orientation in narrow fin MuGFETs
Chi-Woo Lee, A. Afzalian, Ran Yan, Nima Dehdashti, J.P. Colinge, Weize Xiong
[Abstracts of the 14th International Symposium on the Physics of Semiconductors and Applications (ISPSA), Jeju, Korea, p. 282 (2008)]

    Year 2007Equivalent Circuit Based Non-linear Microwave Model for FinFETs
Equivalent circuit based non-linear microwave modelling is studied for the case of FinFET devices. Firstly, an accurate multi-bias small signal equivalent circuit is extracted and then used for building a non-linear full blown lookup table model. Subsequently, an alternative model implementation, which is based on empirical functions, has been investigated. A fully validation of the extracted non-linear models is achieved by comparing their simulation results with large signal measurements.
G. Crupi, D. M. M.-P. Schreurs, I. Angelov, A. Caddemi and B. Parvais
[ISMOT 2007]

Understanding the optimization of sub-45nm FinFET devices for ESD applications
ESD performance of advanced FinFETs shows a delicate sensitivity to device layout and to processing. Thermal issues are experimentally correlated to gate length, fin width, electrical operation mode and are investigated by TCAD simulation. S/D implant conditions, silicide blocking, and selective epitaxial growth are studied. Reasonable ESD performance is demonstrated while margins between success and failure seem to be very narrow.
D. Trémouilles, S. Thijs, C. Russ, J. Schneider, C. Duvvury, N. Collaert, D. Linten, M. Scholz, M. Jurczak, H. Gossner, G. Groeseneken
[29th Electrical Overstress/Electrostatic Discharge Symposium, 2007, pp. 7A.5-1-7A.5-8]

ESD protection for sub-45 nm MugFET technology
From the design point of view, while such technology options may result in increased transistor performance, the ability to achieve sufficient product reliability is to be addressed. Among the industry accepted reliability requirements, electrostatic discharge (ESD) reliability assessment is the focus of this work.
M.I. Natarajan, S. Thijs, D. Tremouilles, D. Linten, N. Collaert, M. Jurczak, G. Groeseneken
[14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, pp. 159-164]

A Quantum Definition of Threshold Voltage in MuGFETs
The dependence of threshold voltage on device dimensions and number of gates is analyzed. A new definition of threshold voltage, based on quantum-mechanical considerations, is proposed.
Se Re Na Yun, Chong Gun Yu, Jong-Tae Park, Chi-Woo Lee, D. Lederer, A. Afzalian, Ran Yan, J.P. Colinge
[Proceedings IEEE International SOI Conference, pp. 137-138, (2007)]

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET
The origin of the large Vt shift observed in planar FDSOI is the creation of negative charge states in the BOX by F implant. F implant is a suitable approach for planar FDSOI SoC integration with single WF metal gate, but NOT for MuGFETs. F implant degrades electron mobility and the degradation is a function of F dose. The hole mobility is unaffected by F implant.
W. Xiong, C.H. Hsu, C.R. Cleavelin, M. Ma, P. Patruno, C-W. Lee, R. Yan, D. Lederer, A. Afzalian, J.P. Colinge
[Proceedings IEEE International SOI Conference 2007, pp. 35-36, (2007)]

Multi-Gate SOI MOSFET Operations in Harsh Environments
This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.
W. Xiong, C. R. Cleavelin, C.H. Hsu, M. Ma, T.Schulz, K. Schruefer, P. Patruno, J.P. Colinge
[Proceedings IEEE International SOI Conference, pp. 29-30, (2007)]

Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer
Multiple-gate-MOSFETs (MuGFET) have better short-channel effects (SCE) control than planar MOSFET and MuGFETs are good candidates to replace planar bulk MOSFET for low power applications. A key feature in the MuGFETs is the recess and undercut of the fins in the buried oxide. Undercut improves gate control of the channel at fin and BOx interface, but also undermines the fin stability, and increases susceptibility to gate etch defects. This paper introduces SOI wafers with nitride buried dielectric that eliminates the undercut, while maintaining good gate control of the channel through higher buried insulator dielectric constant.
P. Patruno, M. Kostrzewa, K. Landry, W. Xiong, C. R. Cleavelin, C. H. Hsu, M. Ma, J. P. Colinge
[Proceedings IEEE International SOI Conference, pp. 51-52, (2007)]

3D Simulation of Doping Fluctuation Effects in Trigate FETs
Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, Aryan Afzalian, Chi-Woo Lee, J.P. Colinge
[Comsol Conference, Grenoble, France, Oct. 2007]

Gate induced floating body effects in TiN/SiON and TiN/HfO₂ gate stack triple gate SOI nFinFETs
In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO₂ gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias (V_BG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance (g_mf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages (V_FG) around 0.8 V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in g_mf is also found in TiN/HfO₂ devices for V_FG around 1.1 V.
Under the accumulation V_BG conditions in which FBEs are observed, front gate switch drain current (I_D) transients are also appreciated. Interestingly, a change in the shape of I_D transients is observed for V_FG conditions in which EVB majority carriers are injected into the floating fin. The I_D transients, as well as the second peak of g_mf and other FBEs, are found to gradually diminish for strong accumulation V_BG conditions or reduced geometry dimensions.
J.M. Rafí, E. Simoen, A. Mercha, N. Collaert, K. Hayama, F. Campabadal, C. Claeys
[Solid-State Electronics Vol. 51, Issue 9, pp. 1201-1210]

Simulation of fluorine implant effects in metal-gate FD-SOI and MuGFETs
Fluorine (F) implantation creates negative charges at the Si/SiO₂ interface in FDSOI transistors[1]. This paper describes simulation of the influence of F Implant on Threshold Voltage (Vth) for Metal Gate FDSOI and MuGFETs using FEMLABⓇ. The origin of the large Vth shift observed in planar FDSOI due to is the creation of negative charge states in the BOX by the F implant. F implant is a suitable approach for planar FDSOI SoC integration with single work function (WF) metal gate, but NOT for MuGFETs.
Chi-Woo Lee, D. Lederer, A. Afzalian, Ran Yan, J.P. Colinge
[Proceedings IEEK 2007 Summer Conference, Korea (2007)]

Solid phase epitaxy versus random nucleation and growth in sub-20 nm wide fin field-effect transistors
The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20 nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20 nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50 nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ~25 nm of the fin, despite being only ~25 nm from the crystalline silicon seed.
R. Duffy, M. J. H. Van Dal, B. J. Pawlak, M. Kaiser, R. G. R. Weemaes, B. Degroote, E. Kunnen and E. Altamirano
[Applied Physics Letters, Vol. 90, Issue 24]

Carrier lifetime analysis in thin gate oxide FD-SOI n-MOSFETs by gate-induced drain current transients
The drain current (I_D) transients by switching the biasing condition are examined in FD-SOI MOSFETs with negative biased back gate voltage (V_BG). Special attention is paid to the influence of the gate-induced charge/discharge of the floating body on the I_D transient. The I_D transient appears not only by switching the front gate voltage (V_FG) but also by switching V_BG. It is also shown that the analysis of a small V_FG step transient is useful to examine the lifetime under different bias conditions. All the results can be explained by the transitional change of I_D − V_FG characteristics at different body-charge conditions.
K. Hayama, K. Takakura, H. Ohyama, J. M. Rafí, A. Mercha, E. Simoen, C. Claeys
[Journal of Materials Science: Materials in Electronics, Vol. 19, Issue 2, pp. 161-165]

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs
The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.
J. M. Rafí, E. Simoen, A. Mercha, K. Hayama, F. Campabadal, H. Ohyama, C. Claeys
[Microelectronic Engineering Vol. 84, Issues 9-10, pp. 2081-2084]

Multi-gate SOI MOSFETs
This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices.
J.P. Colinge
[Microelectronic Engineering, Vol. 84 (9-10), pp. 2071–2076, 2007 (Invited paper at INFOS 2007)]

Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications
MuGFET structure improves local transistor mismatch comparedto planar bulk MOSFET. This enables further SRAM cell sizereduction. GIDL current is well controlled even with a mid-gapmetal gate. MuGFETs have low subthreshold leakage if Lg/Wsiratio is kept above 1.5. The advantage of MuGFET subthresholdleakage suppression is even more pronounced at highertemperatures. Furthermore MuGFETs are compatible with localstrain techniques to improve carrier mobility. The aforementionedqualities, along with low manufacturing cost of single mid-bandgapmetal gate, make MuGFET a good candidate to replace planarbulk MOSFET for Low-Power Applications.
by Weize Xiong, C. Rinn Cleavelin, Che-Hua Hsu, Mike Ma, K. Schruefer, Klaus Von Armin, T. Schulz, I. Cayrefourcq, C. Mazure, P. Patruno, M. Kennard, Kyoungsub Shin, Xin Sun, Tsu-Jae King Liu, K. Cherkaoui and J.P. Colinge
[Electrochemical Society Transactions, Vol. 6 (4), pp. 59-69, 2007]

Evaluation of triple-gate FinFETs with SiO₂–HfO₂–TiN gate stack under analog operation
This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
M.A. Pavanello, J.A. Martino, E. Simoen, R. Rooyackers, N. Collaert, C. Claeys
[Solid-State Electronics Vol. 51, Issue 2, pp. 285-291 ]

Subthreshold channels at the edges of nanoscale triple-gate silicon transistors
The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50×60×35 nm3. Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect.
H. Sellier, G. P. Lansbergen, J. Caro, S. Rogge, N. Collaert, I. Ferain, M. Jurczak and S. Biesemans
[Applied Physics Letters 90, 073502]

Quantum-Mechanical Effects in Nanometer Scale MuGFETs
Se Re Na Yun, Chong Gun Yu, Jong Tae Park, and J.P. Colinge
[Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), pp. 29-32, 2007]

    Year 2006Spacer defined FinFET: Active area patterning of sub-20 nm fins with high density
We present a method to obtain Si-fins with a critical dimension (CD) below 20 nm, separated by a minimum distance of 25 nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350 nm pitch resist pattern defined by 193 nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200 mm wafer. The average CD is 17 nm in the center of the wafer and 18 nm at the edge. The LWR is 3 nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H₂ anneal) further reduce the CD to 13 nm.
B. Degroote, R. Rooyackers, T. Vandeweyer, N. Collaert, W. Boullart, E. Kunnen, D. Shamiryan, J. Wouters, J. Van Puymbroeck, A. Dixit, M. Jurczak
[Microelectronic Engineering Vol. 84, Issue 4, pp. 609-618]

    Year 2004Processor benchmarks: Intel versus AMD = SOI power reduction
The power consumption of the Athlon 64 is lower than that of the Pentium 4 thanks to AMD's use of Silicon-on-Insulator (SOI) technology
[ZDNet.co.uk]