The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness).
The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors (planar & non-planar), ESD structures, Kelvin structures and various test circuits (Ring Oscillators, loaded gates, Current Mirrors, OP-AMPs, SRAM cells, and reliability test sites).
Fully functional FinFET (two gates) devices have been demonstrated on this wafer and yield achieved is more than 90% functional sites. Tri-Gate devices were also built with the same test reticle and are also showing very promising results.
Near ideal DIBL and Sub-Threshold Slope were measured. Device Ion/Ioff data are meeting or exceeding 65nm node targets for High Performance Logic, Low Operating Power and Low Standby Power applications. Other key electrical data for the devices and circuits have been achieved or are close to target goals •