SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications.
When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to:
• the combination of a lower junction capacitance,
• an increased drive current during transition of the gates due to dynamic capacitive coupling
• and an improved drivability of gates using stacked transistors (NAND, NOR, etc.).
The total power consumption includes:
• static power (Pstat),
• internal power dissipated in the gates (Pint)
• and external power (Pext) dissipated in the wiring loads.
Pext is not reduced when switching from bulk to SOI as the interconnections remain identical; the best way to reduce it is to decrease Vdd. As SOI is faster than bulk, Vdd may be reduced to achieve the same speed performance (e.g., clock frequency of the targeted application); Pext is then reduced proportionally to Vdd2.
By reducing Vdd not only Pext is reduced but also Pint and Pstat, then Ptot is globally reduced. Pstat combines drain-source current and gate leakage, reducing Vdd decreases these two leakage components •