SOI for RF & Low Power ICs
Posted date : Apr 18, 2005

When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management.

The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves significantly the high- frequency behavior of the chip: first, because the buried insulating layer reduces part of the electromagnetic field propagation; second, because bonded SOI technology enables the use of a highly resistive (intrinsic silicon) handle wafer, dramatically reducing both resistive losses and crosstalk.

“High resistivity SOI” substrates open new perspectives for RF & SoC circuit designers. Functions (e.g., antenna switch) usually requiring expensive III-V compounds can now be integrated on silicon, reducing the overall system cost with comparable performance and a higher integration level. Denser chip layouts are also achievable thanks to insulation improvement (see Figure 2).

SOI also enables processed top layer transfer onto electronically inert substrates, (e.g., glass), further improving the RF performance.

As traditional benefits of SOI CMOS technology also include the speed versus power-consumption trade-off, this designates SOI as the ideal platform for low-power RF systems. It is compatible with lateral bipolar transistors integration and with future transistor architectures like FinFETs •

Figure 1: RF circuit on bulk

Figure 2: RF Circuit on SOI using High Resistivity (HR) Substrate

About the author