Strained SOI engineered devices and FinFETS (including modified structures such as Multiple Gate FETs (MUGFETS) and Tri-Gates) are among the hottest research topics. Here are some highlights built on SOI or strained SOI substrates.

Strained SOI engineered devices and FinFETS (including modified structures such as Multiple Gate FETs (MUGFETS) and Tri-Gates) are among the hottest research topics. Here are some highlights built on SOI or strained SOI substrates.

From the June 2006 Symposium on VLSI Technology:

High-performance Tri-Gate Demonstrated
(by J.Kavalieros et al., Abstract p.62)

Intel presented a high-performance Tri-Gate transistor in which high-k gate dielectric, metal gate, and strain are all implemented. Thanks to low channel-doping, the mobilities of electrons and holes in the (110) sidewall exceeded the values in conventional (100) planar transistors. Operation of an SRAM cell was also demonstrated with 1.5 times improved drive current, showing the promise of Tri-Gate as next-generation technology.

A First MUGFET Using Super Critical Strained SOI (SC-sSOI)
(by N.Collaert et al., Abstract p.64)

Researchers from TI, IMEC and Soitec detailed performance results for the first, tall triple-gate MUGFETS with fin widths down to 20 nm fabricated for the first time on SC-sSOI. Current drive was boosted 80% for long channel nMOS devices, and an additional 35% for short channel devices using Contact Etch Stop Layers (CESL).

Integration of FinFET for 32 nm Technologies and Beyond
(by H.Shang et al., Abstract p.66)

IBM identified the integration issues of FinFETs and provided solutions for the 32 nm technology node and beyond. Multiple fins (>2) at a 120 nm pitch were formed by e-beam lithography for enhancing the area efficiency. A reduced halo greatly suppressed the threshold voltage variation. A new FinFET design using a selective epitaxial process to merge individual fins was proposed.

Strain Maintained at 25 nm Gate-Length FD-SOI
(by F.Andrieu et al., Abstract p.168)

CEA/Léti, IMEP, ST, Freescale and Soitec researchers presented the first performance of sSOI for short and narrow FD-SOI NMOS transistors integrated with a TiN/HfO2 gate stack. They reported a +16% drive current improvement on a 25 nm gate length (among the best ever reported for short substrate-induced strained devices).

Global and Local Strain Combined to Give the Best Performance
(by A.VY. Thean et al., Abstract p.164)

Freescale and Soitec presented a biaxial-uniaxial hybridized strained CMOS technology, in which the biaxial strain in sSOI (strained SOI) is locally converted to uniaxial strain by selective relaxation of strain, with the addition of a dual-stress nitride capping layer and embedded SiGe source/drain. They obtained nFET/pFET IDsat enhancements as high as 27%/36% for sub-40 nm devices, demonstrating the superior scalability of this technology over pure biaxial and single uniaxial strained technologies.

Ring Oscillator Operated with Record- Fast 3ps in Strained SOI
(by H.Yin et al., Abstract p.94)

Integrating various stress techniques in sSOI, IBM researchers found that sSOI gave the highest performance ever achieved. In PFET, a carefully optimized SiGe-embedded source/drain structure, brought about a 35% enhancement of the drive current. A ring-oscillator delay of 3ps has been obtained at Vds=1.1V, at a leakage current of 1 µA.

Sub-5nm Gate-Length All-Around Gate FinFET
(H.Lee at al., Abstract p.70)

KAIST demonstrated the ultimate scaling of FinFETs by fabricating a 5 nm gate-length allaround gate FinFET. The fin width was made as thin as 3 nm to suppress the short channel effect. The fabricated device operated at room temperature with good on-off behavior, which was well reproduced by device simulation.

From the International Solid-State Circuits Conference (ISSCC):

500 Devices: A First in Multi-Gate FET Circuit Design
With an eye toward SoC requirements in sub-45nm CMOS technologies, Infineon, TI, ATDF and Soitec presented the first digital and analog FinFET and Triple-Gate circuits with a complexity of up to 500 devices.

MUGFET Circuit Design Tutorial
Infineon presented a tutorial covering MUGFET circuit design. TI, ATDF, RWTH Aachen, Soitec, IMEC and the Technical University of Munich were acknowledged as contributors.

From the SEMATECH Surface Preparation and Cleaning Conference (Knowledge Series):

Cleaning and Characterizing MUGFET Structures
A team including researchers from TI, K-T, Infineon, Soitec and FSI looked at ways to reduce pre-existing defects in MUGFETs through automated detection, inspection and classification.

In IEEE Electron Device Letters:

UC Davis, TI, Infineon and Soitec researchers joined forces on the publication of a series of papers exploring processing parameters and the relationship between temperature and mobility in Tri-Gate SOI MOSFETS.

In Nature:

Relaxed, Free-Standing sSOI Nanomembranes
An article by University of Wisconsin–Madison and Soitec demonstrates a versatile method for controlling strain. The membrane fabrication technique enables elastic strain sharing and elimination of defect formation. The technology opens a potential new path to complex, multiple-layer structures.
Nature Materials 5, 388-393 (01 May 2006)

From EuroSOI 2006:

Best Paper Addresses Simulation Techniques
The winner of the EuroSOI 2006 Best Paper Award was a team from the University of Granada, Spain, which developed a complete numerical simulator for electrostatic characteristics of multiple-gate SOI MOSFETS, including corner rounding.

HR SOI for Low-Cost RF
A team lead by STMicroelectronics presented a paper on CMOS-passive component integration, concluding, “…HR SOI seems to be a good candidate for the coming year to address both low-cost and low-power mass market CMOS digital and RF/MMW applications.”

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